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VLSI Physical Design and Formal Verification

This group works on Error Correction and Fault-Tolerance, VLSI Design, Logic Synthesis and Testing, Physical Design of Microchips, Embedded Systems, System-on-a-chip, Electronic Design Automation and Low-Power Architecture, Formal Verification of Hardware and Software.

Group Members


Members Designation
  • Dr. Bhargab B. Bhattacharya
  • Professor
  • Dr. Susmita Sur-Kolay
  • Professor
  • Dr. Ansuman Banerjee
  • Assistant Professor
  • Debasri Saha
  • Senior Research Fellow
  • Manjari Pradhan
  • Junior Research Fellow
  • Bapi Kar
  • Project Linked Fellow
  • Sandip Banerjee
  • Project Linked Fellow
    External collaborators Affiliation


    Publications (by year)


    2014 2013 2012 2011 2010 2009 2008

    2011

    Journals

    1. Hafizur Rahaman, Dipak K. Kole, Debesh K. Das, Bhargab B. Bhattacharya,
      Fault diagnosis in reversible circuits under missing-gate fault model,
      Computers & Electrical Engineering, 37(4): 475-485 (2011)
    2. Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Bhargab B. Bhattacharya, Saraju P. Mohanty
      A Routing-Aware ILS Design Technique,
      IEEE Trans. VLSI Syst., 19(12): 2335-2338 (2011)
    3. Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay
      Floorplanning for Partially Reconfigurable FPGAs,
      IEEE Trans. on CAD of Integrated Circuits and Systems, 30(1): 8-17 (2011)
    4. Pritha Banerjee, Debasri Saha, Susmita Sur-Kolay
      Cone-based placement for field programmable gate arrays,
      IET Computers & Digital Techniques, 5(1): 49-62 (2011)

    Conferences

    1. Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya,
      Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects ,
      Asian Test Symposium, 2011: 297-302.
    2. Ayan Datta, Charudhattan Nagarajan, Susmita Sur-Kolay,
      TSV-aware Scan Chain Reordering for 3D IC,
      ISVLSI, 2011: 188-193.
    3. Debasri Saha, Susmita Sur-Kolay,
      SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection,
      VLSI Design, 2011.
    4. Anvesh Komuravelli, Srobona Mitra, Ansuman Banerjee, Pallab Dasgupta,
      Backward Reasoning with Formal Properties: A Methodology for Bug Isolation on Simulation Traces,
      Asian Test Symposium, 2011: 238-243.
    5. Anvesh Komuravelli, Srobona Mitra, Ansuman Banerjee, Pallab Dasgupta,
      Backward Reasoning with Formal Properties: A Methodology for Bug Isolation on Simulation Traces,
      Asian Test Symposium, 2011: 238-243.
    6. Ansuman Banerjee,
      Requirement Evolution Management: A Systematic Approach,
      ISVLSI, 2011: 150-155.