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**Selected Publications - Journals/Edited Volumes **

* *

97. S. Roy, B. B. Bhattacharya, and K.
Chakrabarty:

Optimization of dilution and mixing of biochemical samples
using digital microfluidic biochips,

* IEEE Transactions on Computer-Aided Design* *of Integrated Circuits
and Systems* *(TCAD)*,

2010 (in press).

96. Z. Chen, S. C. Seth, D.
Xiang, and B. B. Bhattacharya:

PVT: Unified reduction of test power, volume, and test time
using double-tree scan

architecture, *Journal of Low Power Electronics (JOLPE)*,
vol. 6, no. 3, October 2010 (in press).

95. M. Dutt, A. Biswas, P.
Bhowmick, and B. B. Bhattacharya:

On finding an orthogonal convex skull of a digital object, *International
Journal of Imaging *

* Systems and Technology*, 2010 (in press; earlier version appeared as paper
# 84).

94. A. Biswas,
S. Pal, P. Bhowmick, and B.B. Bhattacharya:

Geometric analysis and efficient
indexing of digital documents, In

*Machine
Learning Techniques for Adaptive Multimedia Retrieval: Technologies, *

* Applications and Perspectives*, Ed.
C.-H. Wei, IGI Global, USA, 2010 (in press).

93. S. Pal, P. Bhowmick, A. Biswas, and B.
B. Bhattacharya:

Understanding digital documents using Gestalt properties of
isothetic components,

*International Journal of Digital
Library Systems*, vol. 1, no. 3, pp. 1-25, 2010.

92. S. C. Nandy, K. Mukhopadhyaya,
B. B. Bhattacharya:

Recognition
of largest empty orthoconvex polygon in a point set, *Information
Processing *

* Letters*, vol.
110, pp. 776-752,
2010.

91. A. Biswas, P.
Bhowmick, and B. B. Bhattacharya:

Construction of isothetic covers of a digital object: A
combinatorial approach,

*Journal of Visual Communication and
Image Representation*, vol. 21, pp. 295–310, 2010.

90.
S. Majumder, S. C. Nandy, and B. B. Bhattacharya:

Separating multi-color points on a plane with fewest
axis-parallel lines, *Fundamenta** *

* Informaticae*, vol. 99, issue 3, pp.
315-324, 2010.

89. D. Mitra, S.
Sur-Kolay, B. B. Bhattacharya, S. Kundu, A. Nigam, and S. K. Dey:

Test pattern generation for droop faults, *IET Computers
& Digital Techniques*,* *vol. 4, issue

4, pp. 274-284, 2010.

87. S. Bera, P. Bhowmick, and B. B. Bhattacharya:

Detection of circular arcs in a
digital Image using chord and sagitta properties,

*Lecture Notes in Computer
Science* (LNCS), Springer, vol. 6020, pp. 69-80, 2010 (Selected

papers from GREC
2009).

86. S. Pal, P. Bhowmick, A. Biswas, and B. B. Bhattacharya

**GOAL**: Towards understanding
of **g**raphic **o**bjects from **a**rchitectural to **l**ine
drawings,

*Lecture Notes in Computer
Science* (LNCS), Springer, vol. 6020, pp. 81-92, 2010 (Selected

papers from GREC
2009).

85. P. Bhowmick, S. Bera, and B. B. Bhattacharya:

Digital circularity and its
applications, *Invited Paper, *13th International Workshop on

Combinatorial Image Analysis: (IWCIA), *Lecture Notes in
Computer Science* (LNCS),

Springer, vol. 5852, pp. 1-15, 2009.

84.
A. Biswas, M. Dutt, P. Bhowmick, and B. B. Bhattacharya:

On
finding an orthogonal convex skull of a digital object, In *Progress in
Combinatorial *

* Image Analysis *(Ed. P. Wiederhold and R. P. Barneva), Research
Publishing Services,

Singapore, pp. 25-36, November 2009.

83. P. Bhowmick, R. K. Pradhan,
and B. B. Bhattacharya:

Approximate matching of digital point sets using a novel angular tree,

* IEEE Transactions on Pattern Analysis and Machine
Intelligence *(TPAMI),

vol. 31, issue 5, pp. 769-782, May 2009.

82. H. Rahaman,
D.K. Das, and B. B. Bhattacharya:

Testable
design of AND–EXOR logic networks with universal test sets,

*Computers
and Electrical Engineering*, vol. 35, pp. 644-658, September 2009.

81. P. Bhowmick and B. B. Bhattacharya:

Real polygonal covers of digital discs - some theories and
experiments,

*Fundamenta** Informaticae*, vol. 91, issue 3-4, pp. 487-505, 2009.

80. B. B.
Bhattacharya, S. Sur-Kolay, S. C. Nandy, and A. Bagchi (Edited):

Algorithms,
Architectures, and Information Systems Security, *Statistical Science
and *

* Interdisciplinary Research Series, vol. 3,* World Scientific,
Singapore, 2009.

79. B. B.
Bhattacharya, S. C. Seth, and S. Zhang:

Low-energy pattern generator for random testing*, *In* Algorithms, Architectures, and *

* Information Systems Security*, (Statistical Science and
Interdisciplinary Research, vol. 3),

World Scientific, Singapore, Chapter 8, pp. 117-138, 2009.

78. P. Bhowmick and B. B.
Bhattacharya:

Removal
of digitization errors in fingerprint ridgelines using B-splines, *Pattern
Recognition*,

vol. 42, issue 3, pp. 465-474, March 2009.

77. D. Mitra, S.
Sur-Kolay, and B. B. Bhattacharya:

On droop sensitivity of stuck-at fault tests, *IET Computers & Digital Techniques*

vol. 3, issue 2, pp. 175-193, March 2009.

76. I. Saha, B. B. Bhattacharya,
S. Zhang, and Sharad C. Seth:

Planar straight-line embedding of double-tree scan architecture on
a rectangular grid,

*Fundamenta Informaticae*, vol. 89, issue 2-3, pp.
331-344, 2008.

75. A. Biswas, P. Bhowmick, and B. B. Bhattacharya:** **

Multigrid
shape codes and their applications to image retrieval, *Electronic Letters on *

* Computer Vision and Image Analysis
(ELCVIA)*, vol. 7(2), pp. 62-75, 2008.

74. P. Bhowmick, A. Biswas, and B. B.
Bhattacharya:

Thinning-free
polygonal approximation of thick digital curves using cellular envelope,

*Electronic
Letters on Computer Vision and Image Analysis (ELCVIA)*, vol. 7(2),

pp. 76-95, 2008.

73. Hafizur Rahaman, Debesh
K. Das, and B. B. Bhattacharya:

An
adaptive BIST design for detecting multiple stuck-open faults in a CMOS complex
cell,

*IEEE Transactions on
Instrumentation and Measurement**,
*vol. 57, no. 12,

pp. 2838-2845, December 2008.

72. *S. K.
Mitra, M. K. Kundu, C. A. Murthy, B. B. Bhattacharya,
and T. Acharya: *

* ***A new probabilistic approach for
fractal based image compression, Fundamenta Informaticae, **

** **vol. 87, no. 3-4, **pp.
417-433, 2008.*** *

71. A. Bishnu, P. Bhowmick, B. B. Bhattacharya, M. K. Kundu, C. A. Murthy, and T. Acharya:

Hardware architecture for ridge extraction in fingerprints, In *Advances in Intelligent *

*Information Processing: Tools and Applications *(Statistical Science and
Interdisciplinary Research, vol. 2), World
Scientific, Singapore, pp. 213-242, 2008.

70. A. Biswas, P. Bhowmick, and B. B. Bhattacharya:

Archival image indexing with connectivity features using
randomized masks, *Applied Soft *

* Computing* (Elsevier), vol. 8, issue 4, pp. 1625-1636, Sept. 2008.

69. S. Majumder and B. B.
Bhattacharya:

On the density and
discrepancy of a 2D point set with applications to thermal analysis of

VLSI Chips,
*Information Processing Letters *(IPL), vol. 107, no. 5, pp. 177-182,
August 2008.

68. P. Bhowmick and B. B.
Bhattacharya:

Number-theoretic interpretation and construction of a digital
circle, *Discrete Applied *

* Mathematics *(Elsevier),* *vol. 156, issue 12, pp.
2381-2399, June 2008.

67. P. Bhowmick and B. B.
Bhattacharya:

** **Fast polygonal approximation of digital
curves using relaxed straightness

properties,** ***IEEE Transactions on Pattern
Analysis and Machine Intelligence *

* *(TPAMI), vol. 29, no. 9, pp. 1590-1602, September 2007.

66. S. Banerjee, D.
Roy Chowdhury, and B. B. Bhattacharya:

A programmable
built-in self-test for embedded memory cores,

* *(Invited paper),* IETE Technical Review*, vol. 24, no. 4, pp.
287-311, July-August 2007.

65. S.
Banerjee, D. Roy Chowdhury, and B. B. Bhattacharya:

Layout-aware ILS design technique, in *Progress in* *VLSI Design
and Test *

* *(Ed. S. Sur-Kolay, et al.), Elite Publishing, New Delhi, pp. 61-71,
2007.

64. S.
Majumber, B. B. Bhattacharya, and S. M. A. Jafri:

Reducing crossing number of multi-color rectilinear Steiner trees using
monochromatic

partitioning, In *Advances in Computer
Science and Engineering: Reports and Monographs*,* *

* *vol. 2: Innovative Applications of Information Technology for the
Developing World

(Ed. L. M. Patnaik, et al.), World Scientific, Singapore, pp. 73-77, July
2007.

63. A.
Bishnu and B. B. Bhattacharya:

Stacked Euler Vector (SERVE): A gray-tone image feature based
on

bit-plane augmentation, *IEEE Transactions on Pattern
Analysis and *

*Machine Intelligence *(TPAMI), vol. 29, no. 2, pp.
350-355, February 2007.

62. H. Rahaman, D. K. Das,
and B. B. Bhattacharya:

Testable design of digital summation
threshold logic (DSTL) array for

synthesis of symmetric functions, *International
Journal of Computers *

* and Applications*, vol. 29, issue 2, pp.
202-1694 – 202-1704, 2007.

61. S. Banerjee, Dipanwita Roy Chowdhury, and B. B. Bhattacharya:

An efficient scan tree design for compact test pattern set,

*IEEE Transactions on Computer-Aided Design* *of
Integrated Circuits *

* and Systems* *(TCAD)*, vol. 26, no. 7, pp. 1331-1339, July
2007.

60. S. Dey, B. B.
Bhattacharya, M. K. Kundu, A.
Bishnu, and T. Acharya:

A
co-processor for computing the Euler number of a binary image using

divide-and-conquer strategy, *Fundamenta Informaticae*, vol. 76,
no. 1-2,

pp. 75-89, February 2007.

59. S. Majumder, S. Sur-Kolay, B. B. Bhattacharya, and Swarup Das:

Hierarchical partitioning of
VLSI floorplans by staircases,

*ACM Transactions on Design Automation of
Electronic Systems *

*(TODAES)*, vol. 12, January 2007.

58. A. Bishnu, S. Das, S. C. Nandy, and B. B.
Bhattacharya:

Simple algorithms for partial point set
pattern matching under rigid

motion, *Pattern Recognition*,
Elsevier, vol. 39, no. 9, pp. 1662-1671,

Sept. 2006.

57. H. Rahaman, D. Kole, D. K.
Das, and B. B. Bhattacharya:

Detection of bridging faults in reversible circuits, in *Progress
in* *VLSI Design and *

* Test *(Ed. C. P. Ravikumar), Elite Publishing, New Delhi, pp. 384-392, August
2006.

56. H. Rahaman, D. K.
Das, and B. B. Bhattacharya:

* *Mapping
symmetric functions to hierarchical modules for path-delay

fault testability, *Journal of Electronic
Testing - Theory and Applications*

(JETTA), Springer, vol. 22, no. 2, pp.
125-142, April 2006.

55.
G. Paul, S. N. Pradhan, B. B. Bhattacharya, Ajit Pal, and A.
Das:

BDD-based synthesis of logic functions
using adiabatic multiplexers,

*International Journal on Systemics, Cybernetics, and
Informatics*

(IJSCI), vol. 1, pp. 44-49, April 2006.

54. A. Bishnu, B. B.
Bhattacharya, M. K. Kundu, C. A.
Murthy, and T. Acharya:

A pipeline
architecture for computing the Euler number of a binary image,

*Journal of Systems Architecture*, vol. 51, pp. 470-487,
2005.

53.
P. K. Bhunre, A. Bishnu, C. A. Murthy, B. B. Bhattacharya, M.K. Kundu:

A
hybrid data and space partitioning technique for similarity queries on bounded
clusters,

PReMI 2005, *Lecture Notes in
Computer Science*, Springer, Berlin, vol. 3776,

pp. 544-550, 2005.

52.
A. Biswas, P. Bhowmick, and B.
B. Bhattacharya:

Isothetic
polygons of a 2D object on generalized grid, PReMI 2005, *Lecture Notes
in Computer *

* Science*, Springer, Berlin, vol. 3776, pp. 407-412,
2005.

51. A. Bishnu, B. B.
Bhattacharya, M. K. Kundu, C. A.
Murthy, and T. Acharya:

Euler vector
for search and retrieval of gray-tone images,

*IEEE Transactions on Systems, Man*, *and Cybernetics,*
Part B, vol. 35, pp. 801-812, 2005.

50. P. Bhowmick, A. Bishnu,
B. B. Bhattacharya, M. K. Kundu, C. A. Murthy, and

T. Acharya: Determination of
minutiae scores for fingerprint image applications,

*International
Journal of Image and Graphics,* vol. 5, no. 3, pp. 537-571, July 2005.

49. P. Bhowmick and B. B. Bhattacharya:

Approximation
of digital circles by regular polygons, ICAPR (1) 2005, *Lecture Notes
in *

* Computer Science*, Springer, Berlin, vol. 3686, pp. 257-267, 2005.

48. A. Biswas, P. Bhowmick,
and B. B. Bhattacharya:

TIPS:
On finding a tight isothetic polygonal shape covering a 2D object, SCIA
2005,

*Lecture Notes in Computer Science*, Springer, Berlin,
vol. 3540, pp. 930-939, 2005.

47. H. Rahaman, D. K. Das,
and B. B. Bhattacharya:

Synthesis and testing of reversible logic circuits – A survey,
in *Progress in* *VLSI Design and *

* Test *(Ed. C. P. Ravikumar), Elite Publishing, New Delhi, pp. 71-80, 2005.

46. S. Majumder, B. B.
Bhattacharya, V. D. Agrawal, and M. L. Bushnell:

A new classification of path-delay fault
testability in terms of stuck-at faults,

*Journal of Computer
Science and Technology,* vol. 19, no. 6, pp. 955-964, Nov. 2004.

45. S. Majumder, S. C. Nandy, and B. B. Bhattacharya:

* *On
finding a staircase channel with minimum crossing nets in a VLSI floorplan,

*Journal of Circuits, Systems, and Computers* (JCSC), vol.
13, no. 5, pp. 1019-1038, 2004.

44. H. Rahaman, D. K. Das,
and B. B. Bhattacharya:

Testing
of stuck-open faults in Generalized Reed-Muller and EXOR Sum-of-Products

CMOS circuits, *IEE Proceedings
– Computers and Digital Techniques*, vol. 151, no. 1, pp.

83-93, January 2004.

43. S. Das, S. Sur-Kolay, and B. B. Bhattacharya:

Manhattan-diagonal routing
in channels and switchboxes,

*ACM Transactions on Design Automation of
Electronic Systems *(TODAES), vol. 9,

75-104, January 2004.

42. B. B. Bhattacharya, A.
Dmitriev, and M. Gössel:

Zero-aliasing space compaction of test responses using a single
periodic output,

*IEEE Transactions on Computers,* vol. 52, no. 12, pp.
1646-1651, December 2003.

41. A. Bishnu, S. Das, S. C. Nandy, and B. B.
Bhattacharya:

An
improved algorithm for point-set pattern matching under rigid motion, *Algorithms
and Complexity (CIAC):* *Lecture Notes in Computer Science *(LNCS),
vol. 2653, Springer Verlag, Berlin, pp. 36-45, May 2003.

40. S. C. Nandy and B. B.
Bhattacharya:

Finding
an empty staircase polygon of largest area/width in a planar point-set,

* Computational
Geometry - Theory and Applications *(Elsevier)*, *vol. 26, pp. 143-171,

October 2003.

39. N. Das, B. B. Bhattacharya, and S. Bezrukov:

Permutation
routing in optical MIN with minimum number of stages,

*Journal of Systems Architecture *(Elsevier), vol. 48, pp.
311-323, April 2003.

38. D. K. Das, S. Chakraborty
and B. B. Bhattacharya:

* *Universal
and robust testing of stuck-open faults in Reed-Muller Canonical CMOS circuits,

*International Journal of Electronics,* vol. 90, no.
1, pp. 1-11, January 2003.

37. S. Dey, B. B. Bhattacharya, M. K. Kundu, and T.
Acharya:

A simple architecture for computing moments
and orientation of an image,

*Fundamenta
Informaticae,* vol. 52, no. 4, pp. 285-295, Sept.-Oct. 2002.

36. H. Rahaman, D. K. Das, and B. B. Bhattacharya:

BIST design for detecting multiple stuck-open
faults in CMOS circuits

using transition count, *Journal of Computer Science and Technology,*

vol. 17, no. 6, pp. 731-737,
Nov. 2002.

35. B. B. Bhattacharya, A. Dmitriev, M. Gössel, and K. Chakrabarty:

Synthesis of
single-output space compactors for scan-based sequential circuits, *IEEE
Transactions on Computer-Aided Design*, vol. 21, no. 10, pp. 1171-1179, Oct.
2002.

34. P. S. Dasgupta,
P. Pan, S. C. Nandy, and B. B. Bhattacharya:

Monotone
bipartitioning problem in a planar point set with applications

to VLSI floorplanning, *ACM Transactions on
Design Automation of *

* Electronic Systems (TODAES), *vol. 7, no. 2, pp. 231- 248,*
*April 2002.

33. P. S. Dasgupta,
A. K. Sen,
S. C. Nandy, and B. B. Bhattacharya:

Searching
networks with unrestricted edge costs, *IEEE Transactions on Systems,
Man, and Cybernetics*, Part A, vol. 31, no. 6, pp. 497-507, November 2001.

32. S. C. Nandy, B. B. Bhattacharya, and A.
Hernandez-Barrera:

Safety
zone problem, *Journal of Algorithms*, vol. 37, no. 2, pp. 538-569,
November 2000.

31. D. K. Das, U. K. Bhattacharya, and B. B.
Bhattacharya:

Isomorph-redundancy in sequential circuits, *IEEE
Transactions on *

* Computers*, vol. 49, no. 9, pp. 992-997, September 2000.

30. S. Chakrabarty, S. Das, D. K. Das, and B. B.
Bhattacharya:

Synthesis of symmetric functions for path-delay fault
testability,

*IEEE **Transactions on Computer-Aided **Design*, vol. 19, no. 9,

pp. 1076-1081, Sept. 2000.

29. P. S. Dasgupta, S. Sur-Kolay, and B. B.
Bhattacharya:

A unified approach to topology generation and optimal sizing of
floorplans,* *

* IEEE Transactions on Computer-Aided Design,* vol. 17, pp. 126-135,
February 1998.

28. S.C. Nandy and B. B. Bhattacharya:

Maximal empty cuboids among points and blocks, *Computers and
Mathematics with*

* Applications,* Elsevier Science, vol. 36, no. 3, pp. 11-20, 1998.

27. S. C. Nandy, G. N. Nandakumar, and B. B.
Bhattacharya:

Efficient algorithms for
single and two-layer linear placement of parallel graphs,* Computers and
Mathematics with Applications,* Elsevier Science, vol. 34, no. 12,
pp.121-135, 1997.

26. S. Bandyopadhyay, A. Sengupta, and B. B.
Bhattacharya:

A methodology for testing arbitrary bilateral bit-level systolic
arrays,

** ***VLSI Design,*** **vol.
4, no. 3, pp. 253-269, 1996.

25. S.C. Nandy, A. Sinha and B. B. Bhattacharya:

Location of the largest
empty rectangle among arbitrary obstacles, *Lecture Notes in Computer Science
(LNCS),* vol. 880, pp. 159-170, Springer Verlag, Berlin, 1994.

24. S. C. Nandy and B. B. Bhattacharya:

A unified algorithm for finding maximum and minimum object
enclosing rectangles and

cuboids,* Computers and
Mathematics with Applications, *vol. 29, Elsevier, pp. 45-61, 1994.

23. N. Das, B. B. Bhattacharya, and J. Dattagupta:

Hierarchical classification of permutation classes in multistage
interconnection networks,

*IEEE Transactions on Computers,*** **vol. 43, pp.
1439-1444, December 1994.

22. S. Sengupta, K. Mukhopadhyaya, B. B.
Bhattacharya, and B. P. Sinha:

Geometric classification of
triangulations and their enumeration in a convex polygon,** ***Computers
and Mathematics with Applications, *Elsevier Science, vol. 27, no. 7, pp.
99-115, 1994.

21. D. K. Das, S. K. Chakraborty, and B. B.
Bhattacharya:

Irredundant binate realizations
of unate functions, *International Journal of Electronics, *vol. 75, no.
1, pp. 65 -73, 1993.

20. N. Das, B. B. Bhattacharya, and J.
Dattagupta:

Isomorphism of conflict graphs in multistage interconnection
networks and its

applications to optimal routing, *IEEE Transactions on
Computers,* vol. 42,

pp. 665-677, June 1993.

19. D. K. Das, S. K. Chakraborty, and B. B.
Bhattacharya:

Logical redundancies in
irredundant combinational circuits,* Journal of Electronic Testing, Theory and Applications (JETTA),* * *Kluwer Academic Publishers, vol. 4, pp.
125-130, May 1993.

18. S. Ray, S. C. Nandy, and B. B. Bhattacharya:

Dynamic identification
of all maximal empty rectangles in VLSI
layout design using corner stitching, *Journal of Information Science and
Technology,* vol. 2, no. 1, pp. 44-51, October 1992.

17. P. K. Srimani, B. P. Sinha, B. B.
Bhattacharya, and S. Ghose:

Properties of a class of
trivalent network graphs and optimal routing, *Computers and Mathematics with
Applications, * Elsevier Science,
vol. 22, no. 2, pp. 39-47,* *1991.

16. S. C. Nandy, B. B. Bhattacharya and S. Ray:

Efficient algorithms for
identifying all maximal isothetic empty rectangles in VLSI layout design, *Lecture
Notes in Computer Science (LNCS),* vol. 472, pp. 255-269, Springer-Verlag,
Berlin, 1990.

15. B.B. Bhattacharya and S.C. Seth:

Design of parity testable combinational circuits, *IEEE
Transactions on Computers, *

* *vol. C-38, pp. 1580-1584, Nov. 1989.

14. J. S. Deogun and B.B. Bhattacharya:

Via minimization in VLSI routing with movable terminals, *IEEE
Transactions on Computer-Aided
Design, *vol. CAD-8, no. 8, pp. 917-920, Aug. 1989.

13. S. Sur-Kolay and B. B. Bhattacharya:

Inherent non-slicibility of
rectangular duals in VLSI floorplanning,* Lecture Notes in Computer Science (LNCS),* vol. 338, Springer-Verlag, Berlin, pp. 88-107,
1988

12. B. Gupta, B. B. Bhattacharya, and G. C. Basu:

Testable
design of two-dimensional cellular logic arrays for detecting stuck-at and bridging
faults, *Computers and Electrical Engineering, *Pergamon Press, vol.
14, no. 3/4, pp. 65-74, 1988.

11. B. P. Sinha, B. B. Bhattacharya, S. Ghose, and
P. K. Srimani:

A parallel algorithm to compute the shortest path and diameter of
a graph and its VLSI

implementation, *IEEE Transactions on Computers, *vol.
C-35, no. 11, pp. 1000-1004,

Nov. 1986.

10. B. P. Sinha, S. Ghose, B. B. Bhattacharya, and
P. K. Srimani:

A further note on Pascal graphs, *Fibonacci Quarterly, *vol.
24, no. 3, pp. 251-257,

Aug. 1986.

9. B. B. Bhattacharya and B. Gupta:

On the impossible class of faulty functions in logic networks
under short-circuit faults,

*IEEE Transactions on Computers,*** **vol. C-35, pp.
85-90, Jan. 1986.

8. A. Pal
and B. B. Bhattacharya:

Syndrome testable logic design using DSTL arrays for detecting
stuck-at and bridging faults, *IEE Proceedings - Computers and Digital
Techniques, *Part E, vol. 132, pp.251-256, Sept. 1985.

7. B. B. Bhattacharya, B. Gupta, S. Sarkar, and
A. K. Choudhury:

Testable design of RMC networks with universal tests for
detecting stuck-at and bridging faults, *IEE
Proceedings - Computers and Digital Techniques,* Part E, vol. 132, no. 3,
pp. 155-162, May 1985.

6. B. B. Bhattacharya and B. Gupta:

Optimal design of hazard-free and easily testable logic
networks, *International Journal of *

* Systems Sciences,* vol. 16, no. 4, pp. 491-502, April 1985.

5. B. P. Sinha and B. B. Bhattacharya:

On the numerical complexity of bridging faults in logic networks,
*IEEE Transactions on *

* Computers, *vol. C-34, pp. 186-190, Feb. 1985.

4. B. B. Bhattacharya, S. Ghose, B. P. Sinha and
P. K. Srimani:

Heuristic search approach to optimal routing in a distributed
architecture, *Lecture Notes in
Computer Science (LNCS)*, vol. 181, Springer Verlag, Berlin, pp.
152-164, 1984.

3. B. B. Bhattacharya, B. Gupta, S. Sarkar, and
A. K. Choudhury:

Design of EX-OR
sum-of-product networks with universal tests for detecting stuck-at and bridging faults, *Computers and Electrical Engineering,* * *Pergamon Press, vol. 11,

pp. 67-78, * *Nov.
1984.

2. B. B. Bhattacharya and B. Gupta:

Optimal interconnection in digital systems satisfying
concurrency constraints,

** ***International Journal of Systems Sciences,* vol. 15, No. 9, pp. 991-999, 1984.

1. B. B. Bhattacharya and B.
Gupta:

Anomalous effects of a stuck-at fault in a combinational logic
circuit, *Proceedings of the IEEE, *

* *vol. 71, no. 6. pp. 779-780, June 1983.

114. D. Mitra, S. Ghoshal,
H. Rahaman, K. Chakrabarty, and B. B. Bhattacharya:

Testing of digital microfluidic biochips using improved
eulerization techniques and the Chinese

postman problem, *Proc. 19th Asian Test Symposium*
(ATS), IEEE CS Press, 2010 (accepted).

113. S.
Pratihar, S. Pal, P. Bhowmick, A. Biswas, and B. B. Bhattacharya:

Recognition of handdrawn graphs using digital geometric
techniques,

* 12th International Conference on Frontiers in Handwriting
Recognition*
(ICFHR), 2010

(accepted).

112. A. Sarkar,
A. Biswas, P. Bhowmick, and B. B. Bhattacharya:

Word segmentation and baseline detection in handwritten
documents using isothetic covers,

* 12th International Conference on Frontiers in Handwriting
Recognition*
(ICFHR), 2010

(accepted).

111. A. Bishnu,
S. Das, S. C. Nandy, and B. B. Bhattacharya:

A simple algorithm for approximate partial point set pattern matching under
rigid motion,

Proc. WALCOM, *Lecture Notes in Computer Science*, Springer, vol. 5942, pp. 102-112,

February 2010.

110. Z. Chen,
D. Xiang, S. C. Seth, and B. B. Bhattacharya:

A unified solution to scan test
volume, time, and power minimization, *Proc. 23 ^{rd} *

* International Conference on VLSI Design, *IEEE CS Press, pp. 9-14,
January 2010.

109. A. Ghosh,
R. Shah, A. Bishnu, and B. B. Bhattacharya:

Algorithms for biological cell sorting
with a lab-on-a-chip, *Proc. World Congress on Nature *

* & Biologically Inspired Computing,* IEEE CS Press, pp. 104-109,
November 2009.

108. G. Paul,
R. Reddy, J. Ghosh, A. Pal, C. R. Mandal, and B. B. Bhattacharya:

Power-delay efficient technology mapping of BDD-based circuits
using DCVSPG cells

*Proc. 3rd International Design and Test Workshop*
(IDT), IEEE CS Press, pp. 123-129,

Dec. 2008.

107. D. Mitra,
S. Ghoshal, H. Rahaman, B. B. Bhattacharya, D.
Dutta Majumder, K. Chakrabarty:

Accelerated functional testing of digital microfluidic biochips, *Proc.
17 ^{th} Asian Test *

* Symposium (ATS)*, Japan, IEEE CS Press, pp. 295-300, November 2008.

106. A. Biswas, P. Bhowmick, and
B. B. Bhattacharya:

Finding the orthogonal hull of a digital object: A
combinatorial approach,

* Proc. International Workshop on Combinatorial Image Analysis
(IWCIA)*,
Buffalo, USA,

* Lecture Notes in
Computer Science*, vol. 4958, pp. 124-135, Springer, 2008.

105. B. B. Bhattacharya, A. Biswas, P.
Bhowmick, and T. Achraya:

A fast on-chip mean filter requiring only integer operations, *Proceedings
of the *

* IS & T/SPIE 20**th **Annual Symposium on Electronic Imaging, *vol. 6822, 682217,

SPIE VCIP (Visual
Communication and Image Processing), San Jose, USA, January 2008

(Invited Paper).

104. A. Biswas, S. Khara, P. Bhowmick, and B.
B. Bhattacharya:

Extraction of regions of interest from face images using cellular
analysis,

* Proc. ACM Compute *2008, Article No. 15, pp. 1-8, ACM Press.

103. H. Rahaman, D. K. Kole, D.
K. Das, and B. B. Bhattacharya:

On the detection of missing-gate faults in reversible
circuits by a universal test set, *Proc. 21 ^{st} *

* International
Conference on VLSI Design*, **IEEE CS Press**, USA, pp. 163-168,

January 2008.

102. P.
Bhowmick and B. B. Bhattacharya:

GRASP: Geometric recognition of corner-to-corner straight pieces in an
aerial map,

*Proceedings, International Symposium on Data, Information and
Knowledge Spectrum *

* (ISDIKS)*, Kochi, pp. 55-60, December 2007.

101. H.
Rahaman, D. Kole, Debesh K. Das, and B. B. Bhattacharya:

Optimum test set for bridging
fault detection in reversible circuits, *Proc. 16 ^{th} Asian
Test Symposium (ATS)*, Beijing,
IEEE CS Press, pp. 125-128, Oct. 2007.

100. Rajeev Kumar, P. K.
Singh, and B. B. Bhattacharya:

A local search heuristic for biobjective
intersecting geometric graphs,

*Proc. International Conference on Computing: Theory
and *

* Applications, (ICCTA),* IEEE CS
Press, pp. 224-228, March 2007.

99. P. Bhowmick, A. Biswas, and B. B.
Bhattacharya:

ICE : The Isothetic Convex Envelope of a digital object,* *

* Proc. International Conference on Computing:
Theory and Applications *

* (ICCTA),* IEEE CS
Press, pp. 219-223, March 2007

98.
P. Bhowmick, A. Biswas, and B. B. Bhattacharya:

Ranking of optical character prototypes using cellular
lengths,** ***Proc. *

* International Conference on Computing:
Theory and Applications *

* (ICCTA),* IEEE CS
Press, pp. 422-426, March 2007.

97.
A. Biswas, P. Bhowmick, and B. B. Bhattacharya:

Characterization of isothetic polygons for image indexing and
retrieval,** **

** ***Proc. International Conference
on Computing: Theory and Applications *

* (ICCTA)*, IEEE CS
Press, pp. 590-594, March 2007.

96. G. Paul, S. N.
Pradhan, Ajit Pal, and B.** **B. Bhattacharya:

Low-power BDD-based synthesis using dual rail static DCVSPG

logic, *Proc., IEEE Asia Pacific Conference on Circuits and
Systems*,

*(ASPCAS),* IEEE CS Press, pp. 1504-1507, December 2006.

95. P.
Bhowmick, A. Biswas, and B. B. Bhattacharya:

PACE: Polygonal approximation of thick digital curves using

cellular envelope, *Proc. 5th Indian Conference on Computer
Vision, *

* Graphics and Image Processing* *(ICVGIP)*, Lecture
Notes in Computer

Science,
vol. 4338, Springer, pp. 299-310, December 2006.

94. A. Biswas,
P. Bhowmick, and B. B. Bhattacharya:

SCOPE: Shape complexity of objects using isothetic polygonal

envelope, *Proc. 6th International Conference on Advances in Pattern *

* Recognition* *(ICAPR)*, World
Scientific, pp. 356-360, January 2007.

93. P.
Bhowmick, A. Biswas, and B. B. Bhattacharya:

DRILL: Detection and representation of isothetic loosely connected

components without labeling, *Proc. 6th International Conference
on *

* Advances in Pattern Recognition* *(ICAPR)*, World
Scientific, pp. 343-348,

January 2007.

92. Rajeev Kumar, P. K.
Singh, and B. B. Bhattacharya:

Biobjective evolutionary and heuristic
algorithms for intersection of

geometric graphs, *Proc. 8th Genetic and Evolutionary Computation *

* **Conference
(GECCO-2006)*, Seattle, USA, pp. 1689-1696, July 2006.

ACM Press.

91. G. Paul, B.** **B.
Bhattacharya, and Ajit
Pal:

On
finding the minimum test set of a BDD-based circuit, *Proceedings, *

* ACM/IEEE Great Lakes Symposium on VLSI*, pp. 169-172, May 2006, ACM Press.

90. S. Majumder and B. B.
Bhattacharya:

Solving thermal problems of hot chips
using Voronoi diagrams, *Proc. 19 ^{th} International *

* Conference on VLSI Design*,
**IEEE CS Press**, USA, pp. 545-548, January 2006.

**89. S.
Banerjee, D.
Roy Chowdhury**, B. B. Bhattacharya:

** An efficient scan tree design for
compact test pattern set,*** Proc. 19 ^{th} International *

* Conference on VLSI Design*, **IEEE CS Press**, USA, pp. 175-180,
January 2006.

**88. A.
Lahiri, S. Agarwal**, A.
Basu, and B. B. Bhattacharya:

Recovery-based real-time scheduling for battery life
optimization, *Proc. 19 ^{th} International *

* Conference on VLSI Design*, **IEEE CS Press**, USA, pp. 469-472,
January 2006.

*87. D.
Mitra, S. Bhattacharjee, S. Sur-Kolay, B. B. Bhattacharya, S. T. Zachariah, and
*

* S. Kundu:** *

* *Test pattern generation for power supply droop faults,* Proc. 19 ^{th}
International *

* Conference on VLSI Design*, **IEEE CS Press**, USA, pp. 343-348,
January 2006.

86. A. Biswas, P. Bhowmick,
and B. B. Bhattacharya:

MUSC: Multigrid shape codes and their applications to image
retrieval, *Proc. International *

* Conference on Computational Intelligence
and Security* (CIS'2005) Xian, *Lecture Notes in *

* Computer Science, *vol. 3801*, *(sub-series LNAI), Springer,
Berlin, pp. 1057-1063, Dec. 2005.

85. A. Biswas, P. Bhowmick,
and B. B. Bhattacharya:

Reconstruction
of torn documents using contour maps, *Proc. International *

* Conference on Image Processing (ICIP)*, Genoa, Italy, vol. 3, pp.
517-520,

**IEEE CS Press**, USA, Sept. 2005.

84.
**D. Mukhopadhyay, S. Banerjee, D. **Roy
Chowdhury, and B. B. Bhattacharya:

CryptoScan: A secured scan-path
architecture, *Proc. Asian Test Symposium*, **IEEE CS **

** Press**, USA, pp. 348-353, Dec. 2005.

83.
S. Zhang, S. C. Seth, and B. B. Bhattacharya:

Efficient test compaction for
pseudo-random testing, *Proc. Asian Test Symposium*, **IEEE **

** CS Press**, USA, pp. 337-342, Dec.
2005.

82.
S. Majumder and B. B. Bhattacharya:

Density or discrepancy? A VLSI
designer’s dilemma in hot spot analysis, *Proc.* 17^{th}

*Canadian Conference in Computational
Geometry (CCCG), *pp. 167-170, August 2005.

**81. S. Banerjee, D. **Roy Chowdhury, B. B.
Bhattacharya:

**A
programmable built-in self-test for embedded DRAMs, Proc. Int. Workshop
on Memory **

*
Technology, Design, and Testing (MTDT)***, ****IEEE CS Press****, USA,
pp. 58-63, August 2005.**

80. S. Majumder, S.
Sur-Kolay, S. C. Nandy, B. B. Bhattacharya, and B. Chakraborty:

Hot
spots and zones in a chip: A geometrician’s view, *Proc. 18 ^{th} International *

* Conference on VLSI Design*, **IEEE CS Press**, USA, pp. 691-696,
January 2005.

79. S. Zhang, S. C. Seth,
and B. B. Bhattacharya:

On finding consecutive test vectors in a random sequence for
energy-aware BIST design*, Proc. 18 ^{th} International Conference on
VLSI Design*,

January 2005.

78. A. Biswas, P. Bhowmick,
and B. B. Bhattacharya:

CONFERM: Connectivity
Features with Randomized Masks and Their Applications to Image Indexing, *Proc. Fourth Indian Conference
on Computer Vision, Graphics and Image Processing (ICVGIP),* pp. 556-562,
Dec. 2004.

77. P. Bhowmick and B. B.
Bhattacharya:

CODE: An Adaptive
Algorithm for Detecting Corners and Directions of Incident Edges, *Proc. Fourth
Indian Conference on Computer Vision, Graphics and Image Processing (ICVGIP),*

pp. 509-515, Dec. 2004.

76. A. Bishnu, S. Das, S. C.
Nandy, and B. B. Bhattacharya:

Approximate Partial Point Set Pattern
Matching under Rigid Motion, *Proc., Japan Conference on Discrete and
Computational Geometry*, Tokyo, Japan, October 2004.

75.
D. K. Das and B. B. Bhattacharya:

Redundancy and undetectability of faults
in logic circuits: A tutorial, *Progress in* *VLSI Design and Test, *Elite
Publishing, New Delhi*,* pp. 514-526, August 2004,* *

(VDAT Workshop, Mysore).

74.
P. Bhowmick and B. B. Bhattacharya:

Approximate
fingerprint matching using Kd-tree, *Proc. International Conference on Pattern *

* Recognition (ICPR-04)*,
**IEEE CS Press**, USA, vol. 1, pp. 544-547, August 2004.

73. H. Rahaman, D. K. Das, and B. B.
Bhattacharya:

Testable design of GRM network with EXOR-tree for
detecting stuck-at and bridging faults, *Proc. Asia-South-Pacific Design
Automation Conference (ASPDAC)*, **IEEE CS Press**, USA, pp. 224-229, January 2004.

72. H. Rahaman, D. K. Das, and B. B.
Bhattacharya:

Easily
testable realization of EXOR-sum-of-product network for detecting stuck-at and
bridging faults, *Proc. International Conference on VLSI Design*, **IEEE
CS Press**, USA, pp. 487-492, January 2004.

71.
S. Sur-Kolay, P. S. Dasgupta, B. B. Bhattacharya, and S. T. Zachariah:

Physical
Design Trends and Layout-Based Fault Modeling, Tutorial Lecture Notes, *International Conference
on VLSI Design*, January 2004.

70. H. Rahaman, D. K. Das, and B. B. Bhattacharya:

Mapping
symmetric functions to hierarchical modules for path-delay fault testability,
*Proceedings, Asian Test Symposium (ATS)*, **IEEE CS Press**, USA, pp.
284-289, Nov. 2003.

69. S. K.
Mitra, C. A. Murthy, M. K. Kundu, B. B. Bhattacharya, and T. Acharya:

Digital
watermarking using homogeneity in image, *Proc. IEEE TENCON*, 2003.

68.** **B. B. Bhattacharya, S. C. Seth, and S. Zhang:

Double-tree
scan: A novel low-power scan-path architecture, *Proc. International Test
Conference (ITC)*, IEEE CS Press, USA, pp. 470-479, 2003.

67. B. B. Bhattacharya, S. C. Seth, and S. Zhang:

Low-energy
BIST design for scan-based logic circuits*, Proc. International
Conference on VLSI Design*, **IEEE CS Press**, USA, pp. 546-551, January 2003.

66. A. Bishnu, P. Bhowmick, J. Dey, B. B.
Bhattacharya, M. K. Kundu, C. A. Murthy, and

T. Acharya: Combinatorial
classification of pixels for ridge extraction in a gray-scale fingerprint image,
*Proc. Third Indian Conference on Computer Vision, Graphics and Image
Processing (ICVGIP),* Allied Publishers Pvt. Ltd., pp. 451-456, December
2002.

65. P. Bhowmick, A. Bishnu, B. B. Bhattacharya,
M. K. Kundu, C. A. Murthy, and T. Acharya:

Determination of
minutiae scores for fingerprint image applications, *Proc. Third Indian
Conference on Computer Vision, Graphics and Image Processing (ICVGIP),*
Allied Publishers Pvt. Ltd., pp. 463-468, December 2002.

64. A. Bishnu, P. K. Bhunre, B.
B. Bhattacharya, M. K. Kundu, C. A. Murthy, and T. Acharya:

Content-based
Image Retrieval: Related issues using Euler vector, *Proc. IEEE Int.
Conference on Image Processing (ICIP)*, Rochester, **IEEE CS Press**,
USA, vol. II, pp.585-588, Sept. 2002.

63. A. Bishnu, B. B.
Bhattacharya, M. K. Kundu, C. A. Murthy, and T. Acharya:

Euler vector: A combinatorial signature of gray-tone
images, *Proc. Int. *

* Conference on Information Technology - Coding and Computing (ITCC)*,

* ***IEEE CS Press**, USA, pp. 121-127, April 2002.

62. H. Rahaman, D. K. Das,
and B. B. Bhattacharya:

A
new synthesis of symmetric functions, *Proceedings, International Joint
Conference on ASP-DAC and VLSI Design*,
**IEEE CS Press**, USA, pp. 160-165,
January 2002.

61. A. Bishnu, B. B. Bhattacharya, M. K. Kundu, C. A. Murthy, and T.
Acharya:

On-chip
computation of Euler number of a binary image for efficient database search,

*Proc. IEEE
International Conference on Image Processing (ICIP)*, Greece,

**IEEE CS Press**, USA, vol. 3, pp. 310-313, Oct.
2001.

60. D. Majumdar, A. Bishnu, B. B. Bhattacharya, M. K. Kundu, C. A.
Murthy, and T. Acharya: On-chip
Computation of Invariant Moments for Gray-Tone Images, *Intelligent
Computing and VLSI,* **Allied Publishers Ltd.,** New Delhi, India, pp.
173-180, 2001.

59. S. Majumder, S. Sur-Kolay, B. B. Bhattacharya, and S. C. Nandy:

Area (number)-balanced hierarchy of staircase channels with
minimum crossing nets*, *

* Proc. Int. Symposium on Circuits & Systems (ISCAS)*, **IEEE CS Press**, USA,
vol. 5,

pp. 395-398, May 2001.

58. A. Morosov, M. Gössel, K. Chakrabarty, and B. B. Bhattacharya:

Design
of parameterizable error-propagating space compactors for response compaction,

* Proc. 19 ^{th} VLSI Test Symposium (VTS)*,

57. S. K. Mitra, C. A. Murthy, M. K. Kundu, B. B. Bhattacharya, and T.
Acharya:

Fractal
image compression using iterated function system with probabilities, *Proc.
Int. Conference on Information Technology - Coding and Computing*, **IEEE
CS Press**, USA, pp. 191-195, April
2001.

56. B. B. Bhattacharya, A. Dmitriev, M. Gössel, and K. Chakrabarty:

Synthesis
of single-output space compactors with applications to IP cores, *Proceedings,
*

* 5*^{th}* Asia-South-Pacific Design Automation Conference (ASP-DAC)*, **IEEE CS Press**,

* *USA, pp. 496-501, Jan-Feb 2001.

55. D. K. Das, B. B. Bhattacharya, S.
Ohtake, and H. Fujiwara:

Testable
design of sequential circuits with improved fault efficiency, *Proceedings,
14*^{th}* International Conference on
VLSI Design*, **IEEE CS Press**, USA,
pp. 128-133, January 2001.

54. K. Sinha, S. Sur-Kolay, P. S. Dasgupta, and B. B. Bhattacharya:

Partitioning
routing area into zones with distinct pins, *Proceedings, 14*^{th}* International Conference on
VLSI Design*, **IEEE CS Press**, USA,
pp. 345-350, January 2001.

53. D. K. Das, S. Chakrabarti, and B. B. Bhattacharya:

Boolean algebraic properties of fault behavior in logic circuits*,
Proceedings, *

*4*^{th}* International Workshop on
Boolean Problems*, Freiberg, Germany, pp. 143-150,

Sept. 2000.

52. H. Rahaman, D. K. Das,
and B. B. Bhattacharya:

* *Transition
count based BIST for detecting multiple stuck-open faults in CMOS circuits,

* Proceedings, 2 ^{nd}
IEEE Asia Pacific Conference on ASICs (AP-ASIC), *Korea, August 2000.

51. B. B. Bhattacharya, A. Dmitriev, and M. Gössel:

Zero-aliasing space compression using a single
periodic output and its application to testing of embedded cores, *Proceedings, 13 ^{th}
International Conference on VLSI Design*,

50. S. Bhunia, S. Majumder, A. Sircar, S. Sur-Kolay, and B. B.
Bhattacharya:

Topological
routing amidst polygonal obstacles, *Proceedings, 13 ^{th}
International Conference on VLSI Design*,

49. S. Dey, B. B. Bhattacharya, M. K. Kundu, and T. Acharya:

A
fast algorithm for computing the Euler number of an image and its VLSI
implementation,

* Proceedings, 13 ^{th} International Conference on
VLSI Design*,

pp. 330-335, January 2000.

48. S. Dey, B. B. Bhattacharya, M. K. Kundu, and T. Acharya:

Computing orientation of an image by projection method and its
VLSI implementation,

in *Advances in Pattern Recognition and Digital Techniques***
**(Ed.), **Narosa,**

pp. 331-335, 1999.

47. H. Rahaman, D. K. Das,
and B. B. Bhattacharya:

* An adaptive
BIST to detect multiple stuck-open faults in CMOS circuits*, *Proceedings, 4 ^{th} Asia-South-Pacific Design Automation
Conference (ASP-DAC), *

46. S. Majumder, B. B. Bhattacharya, V. D. Agrawal, and M. L. Bushnell:

A
complete characterization of path delay faults through stuck-at faults, *Proceedings,
12 ^{th} *

*International Conference on
VLSI Design*, **IEEE CS Press**, USA,
pp. 492-497, January 1999.

45. S. Das, S. C. Nandy, and B. B. Bhattacharya:

High-Performance
MCM routing: A new approach, *Proceedings, 12 ^{th} International *

* Conference on VLSI Design*, **IEEE CS Press**, USA, pp. 564-569,
January 1999.

44. S. Chakraborty, S. Das, D. K. Das, and B. B. Bhattacharya:

Synthesis
of symmetric functions for path-delay fault testability, *Proceedings, 12 ^{th} International
Conference on VLSI Design*,

43. N. Das, B. B. Bhattacharya, R. Menon, and S. Bezrukov:

Permutation admissibility in shuffle-exchange networks with
arbitrary number of stages,

* Proceedings, 5 ^{th}
International Conference on High Performance Computing*,

42. D. K. Das, S.
Chakraborty and B. B. Bhattacharya:

* *Interchangeable
Boolean functions and their effects on redundancy in logic circuits,

*Proceedings, 3 ^{rd}
Asia-South-Pacific Design Automation Conference (ASP-DAC), *

* ***IEEE CS Press**, USA, * *pp. 469-474,
February 1998.* *

41. D. K. Das, I. Chaudhuri
and B. B. Bhattacharya:

* *Design
of an optimal test pattern generator for built-in self testing of path delay
faults,

* Proceedings, 11 ^{th} International Conference on VLSI Design*, pp. 205-210,

** IEEE CS Press**, USA, January 1998.

40. S. Majumder, S. C.
Nandy, and B. B. Bhattacharya:

* *Partitioning
VLSI floorplans by staircase channels for global routing,* Proceedings, 11 ^{th} *

* Int. Conf. on VLSI
Design*,
pp. 59-64, **IEEE CS Press**, USA, January 1998.

39. S. Das, S. Sur-Kolay and
B. B. Bhattacharya:

Routing of
L-shaped channels, switchboxes, and staircases in Manhattan-Diagonal model,*
Proceedings, 11 ^{th} Int. Conf.
on VLSI Design*, pp. 65-70,

38. D. K. Das, S.
Chakraborty and B. B. Bhattacharya:

* *Universal and robust testing of stuck-open faults in Reed-Muller
Canonical CMOS circuits,

* Proceedings, 3 ^{rd}
Int. Workshop on the Applications of the Reed Muller Expansion in *

* Circuit Design*, Oxford, U. K., pp. 259-268, Sept. 1997.

37. D. K. Das, S. Chakrabarty
and B. B. Bhattacharya:

New
BIST techniques for universal and robust testing of CMOS stuck-open faults,* Proceedings,
10 ^{th} Int. Conf. on VLSI
Design, *pp. 303-308,

36. S. C. Nandy, K. Mukhopadhyaya and B. B. Bhattacharya:

Shooter location problem, *Proceedings, 8 ^{th}
Canadian Conference on *

* Computational Geometry, *pp. 93 - 98, **Carleton
University Press**, Canada, 1996.

35. P. S. Dasgupta, A. K.
Sen, S. C. Nandy and B. B. Bhattacharya:

Geometric bipartitioning
problem and its applications to VLSI, *Proceedings, 9 ^{th} Int. *

*Conf. on VLSI Design*, pp. 400-405, **IEEE CS
Press**, USA, January 1996.

34. D. K. Das, U. K. Bhattacharya and B. B. Bhattacharya:

Isomorph-redundancy in
sequential circuits, *Proceedings, 14 ^{th} IEEE VLSI Test *

*Symposium (VTS), *pp. 463-468, **IEEE CS
Press**,* *USA, 1996.

33. S. Das and B. B.
Bhattacharya:

* *Channel
routing in Manhattan-Diagonal model,* Proceedings, 9 ^{th}
International Conf. on VLSI Design*, pp. 43-48,

32. D. K. Das and B. B.
Bhattacharya:

Does
retiming affect redundancy in sequential circuits?,* Proceedings, 9 ^{th} *

* International Conference
on VLSI Design*, pp. 260-263, **IEEE
CS **

** Press**, USA, January 1996.

31. M. Ghosh, D. Das, B. P.
Sinha and B. B. Bhattacharya:

Fractal graphs : a new class of self-similar network
topologies, *High *

* Performance Computing*, pp. 617-622, **Tata McGraw-Hill**, December

1995.

30. P. S. Dasgupta, S.
Sur-Kolay and B. B. Bhattacharya:

A unified approach to topology generation and area
optimization of

general floorplans,* Digest of Technical Papers, IEEE/ACM
International *

* Conference on Computer-Aided Design
(ICCAD)*,
pp. 712-715,

**IEEE CS Press**, USA, November 1995.

29. D. K. Das and B. B. Bhattacharya:

Testable design of non-scan sequential circuits using extra
logic, *Proceedings, 4 ^{th} Asian Test *

* Symposium (ATS), *pp. 176-182, **IEEE CS
Press**, USA, November 1995.

28. P. S. Dasgupta, S.
Sur-Kolay and B. B. Bhattacharya:

VLSI floorplan generation and area optimization using AND-OR
graph

search,* Proc., 8 ^{th} Int. Conf. on VLSI Design*, pp. 370-375,

** Press**, USA, January 1995.

27. P. S. Dasgupta and B. B.
Bhattacharya:

A best-first search algorithm for channel routing, Proc. *International *

* Computing Congress, *pp. 13-21, **Tata McGraw-Hill**, Dec. 1993.

26. S. Das and B. B. Bhattacharya:

Via minimization in channel routing by layout modification, *Proc.,
6 ^{th} *

* International Conference
on VLSI Design,* p. 109, **IEEE CS Press**,

USA, January 1993.

25. S. Sur-Kolay and B. B. Bhattacharya:

Canonical
embedding of rectangular duals with applications to VLSI floorplanning, *Proceedings,
29 ^{th} ACM/IEEE Design Automation Conference (DAC),* pp. 69-74,

24. S. Bandyopadhyay and B. B.
Bhattacharya:

On the testable design of bilateral bit-level systolic arrays, *Proceedings,
International Test Conference (ITC),*
pp. 1024-1033, **IEEE CS Press**, USA, November 1991.

23. S. Sur-Kolay and B. B. Bhattacharya:

The
cycle structure of channel graphs in nonslicible floorplans and a unified
algorithm for feasible routing order, *Proceedings, International
Conference on Computer Design (ICCD),* pp. 524-529, **IEEE CS Press**,
USA, October 1991.

22. S. Sur-Kolay and B. B. Bhattacharya:

On the family of inherently nonslicible floorplans in VLSI
layout design, *Proceedings,*

* International Symposium on Circuits and Systems (ISCAS),* Singapore, pp. 2850-2853, ** IEEE CS Press**, USA, June 1991.

21. S. Das, S. C. Nandy and B. B. Bhattacharya:

An improved heuristic algorithm for over-the-cell channel
routing, *Proceedings, International Symposium on Circuits and
Systems (ISCAS),* Singapore, pp. 3106-3109, ** IEEE CS Press**, USA, June 1991.

20. K. Gopalakrishnan and B. B.
Bhattacharya:

Non-checkpoints
target faults: how to order them?, *Proceedings, 34 ^{th} Midwest Symposium on Circuits and Systems*,
Monterey, pp. 619 - 622, May 1991.

19. U. Bhattacharya and B.
B. Bhattacharya:

Delay fault testing in combinational circuits: A survey,

* Information Technology*, **Tata McGraw-Hill**, pp. 115 - 125, 1990.

18. S. Bandyopadhyay and B. B. Bhattacharya:

A methodology for testing arbitrary bilateral bit-level systolic
arrays, Proc.,* 24 ^{th} Asilomar Conf. on Signals, Systems and
Computers,*

17. N. Das, B. B. Bhattacharya and J. Dattagupta:

Analysis
of conflict graphs in multi-stage interconnection networks, Proc. *Region
10 *

* Conference on Computer and Communication System (TENCON),* pp. 175 - 179, ** IEEE CS Press**, USA, Sept., 1990.

16. P.K. Srimani, B.P. Sinha, B.B. Bhattacharya
and S. Ghose:

On some problems of trivalent network graphs, Proceedings, *23 ^{rd}
Asilomar Conference on Signals,*

15. W. Ke, S. C. Seth and B. B. Bhattacharya:

A
fast fault simulation algorithm for combinational circuits, *Digest of
Papers,* *IEEE/ ACM
International Conference on
Computer-Aided Design (ICCAD),* pp. 166-169, **IEEE CS Press**, USA, Nov.
1988.

14. B. B. Bhattacharya, J. S. Deogun and N. A. Sherwani:

A
graph-theoretic approach to single row routing problems, *Proc.,* *Int.
Symposium on Circuits and Systems
(ISCAS), *pp. 1437-1440, **IEEE CS Press**, USA, June 1988.

13. J. S. Deogun and B. B. Bhattacharya:

An unified approach to via minimization with movable terminals
in VLSI routing, * Proceedings, 2 ^{nd} International Conference on Computers and
Applications, *Beijing,

pp. 863-869, **IEEE CS Press**, USA, June 1987.

12. B. B. Bhattacharya and S. C. Seth:

On the reconvergent structure of combinational circuits with
applications to compact testing, *Digest of Papers, International Symposium
on Fault-tolerant Computing Systems (FTCS-17),* pp. 264-269, **IEEE CS Press**, USA, 1987.

11. S. C. Seth, B. B. Bhattacharya and V. D. Agrawal:

An exact analysis for efficient computation of random pattern
testability in combinational circuits, *Digest of Papers, International
Symposium on Fault-tolerant Computing Systems *

* (FTCS-16),* pp. 318-323,** IEEE CS Press**, USA, July 1986.

10. B. Gupta, B. B. Bhattacharya and G. C. Basu:

Universal testability of nMOS RMC networks for detecting
physical failures, Proc. *1 ^{st}
*

* International* *Workshop on VLSI Design,* pp. I-1 -I-11, Dec.
1985.

9. P. K. Srimani, B. P. Sinha, B. B. Bhattacharya and S. Ghose:

An efficient distributed algorithm for directed circuits in a graph,
*Proceedings,* * Int. Symp. on* *Circuits and Systems
(ISCAS), *pp. 967-969, **IEEE CS Press**, USA, June 1985.

8. B. B. Bhattacharya, S. Ghose, B. P. Sinha and P. K. Srimani:

A heuristic search approach to optimal routing and some related
properties in trivalent processor network graphs, Proc. *IEEE International
Conference on Computers Systems and Signal Processing,* pp. 525-528, Dec. 1984.

7. B. B. Bhattacharya, S. Ghose, B. P. Sinha and P. K. Srimani:

A parallel algorithm to
compute the diameter of a symmetric graph,* ibid.*, pp. 203-206, Dec. 1984.

6. B. B. Bhattacharya and B. Gupta:

Logical modeling of physical failures and their inherent syndrome
testability in MOS LSI/VLSI networks, *Proceedings, International Test
Conference (ITC-84),* Philadelphia, pp. 847-855,** IEEE CS Press**, USA,
Oct. 1984.

5. B. B. Bhattacharya and B. Gupta:

A graph-theoretic approach to optimal design of static-logic
hazard-free combinational circuits, *Proceedings, International Symposium on
Circuits and Systems (ISCAS), *pp. 1143-1146, **IEEE CS Press**, USA, May
1984.

4. B. B. Bhattacharya and B. Gupta:

Syndrome testable design of combinational networks for detecting stuck-at and bridging
faults, Proc. *International Test Conference (ITC)*, Philadelphia, pp.
446- 452, **IEEE CS Press**, USA, Oct. 1983.

3. S. Ghose, B. P. Sinha, J. Dattagupta, B. B. Bhattacharya and A.
Pal:

Systems diagnosability in composite systems, *Proceedings,
International Symposium on Circuits
and Systems (ISCAS),* Montreal, pp. 1310-1313,** IEEE CS Press**,
USA, May 1983.

2. B. Gupta, B. B. Bhattacharya, and A. K. Choudhury:

A switching theoretic
approach to information compression and its unambiguous retrieval, *Advances
in Information Science and Technology*, vol. II, Indian Statistical
Institute,** ** Calcutta, pp. 155-164,
January 1982.

1. B. B. Bhattacharya, B.
Gupta, and A. K. Choudhury:

1. T. Acharya, B. B. Bhattacharya, P. Bhowmick, A. Bishnu, A. Biswas, M. K. Kundu,

C. A. Murthy, S. Das, and S. C. Nandy:

* Fingerprint
Minutia Matching using Scoring Techniques*,

United States Patent # 7,359,532, issued on April 15,
2008.

2. T. Acharya, B. B. Bhattacharya, P. Bhowmick,
A. Bishnu, J. Dey,

M. K. Kundu, and C. A. Murthy:

* Method
and Apparatus for Providing a Binary Fingerprint Image, *

United
States Patent # 7,136,515, issued on November 14, 2006.

3. T. Acharya, B. B.
Bhattacharya, A. Bishnu, M. K. Kundu, and C. A. Murthy:

*Computing
Euler Number of a Binary Image*,

United States Patent # 7,027,649, issued on April 11, 2006.

4. T. Acharya, B. B. Bhattacharya, P. Bhowmick,
A. Bishnu, J. Dey, M. K. Kundu,

and C. A. Murthy:

* Architecture
for Processing Fingerprint Images, *

United States Patent # 6,795,592, issued on September 21,
2004.

5. T. Acharya, B. B. Bhattacharya, M. K. Kundu, S. K. Mitra, and C. A.
Murthy:

* Method
of Compressing an Image, *

United States Patent # 6,738,520, issued on May 18, 2004.

6. T. Acharya, B. B. Bhattacharya, M. K. Kundu, S. K. Mitra, and C. A. Murthy:

*A
Method for Block-based Digital Image Watermarking, *

United States Patent #
6,707,928, issued on March 16, 2004.

7. T. Acharya, B. B. Bhattacharya, A. Bishnu, M. K. Kundu, and C. A.
Murthy:

*Image
Retrieval using Distance Measure, *

United States Patent # 6,681,060, issued on January 20, 2004.

8. T. Acharya, B. B. Bhattacharya, P. Bhowmick, A. Bishnu, J. Dey, M.
K. Kundu,

and C. A. Murthy:

* Method
and Apparatus to Reduce False Minutiae from a Binary Fingerprint Image, *

US Patent pending (Publication Application # 20030063782,
April 2003).

9. T. Acharya, B. B. Bhattacharya, M. K. Kundu, S. Maity, and C. A.
Murthy:

* Robust
Digital Image Watermarking utilizing a Walsh Transform Algorithm*,

US Patent pending (Publication Application # 20050144456, June 2005).

1. Principal Investigator, *Logic
Extraction and False Path Identification in VLSI Circuits,* funded by **Motorola
India Electronics Ltd.,** Bangalore, 1996-1998.

2. Principal Investigator, *Compilation
and Optimization of Reconfigurable
Processors, *jointly

with **IRISA, France, **& funded by **Indo French Centre
for the Promotion of Advanced **

** Research, **New Delhi, 1999-2002 (Co-PI: B.
P. Sinha, S. Sur-Kolay, and S. Rajopadhye)

3. Co-Principal Investigator, *New
Techniques of Fast Image Compression based on Human Vision System and Geometric
Data Structures,* funded by **Intel
Corporation,** USA, 1998-2003 (Co-PI: M. K. Kundu; Co-I: C. A. Murthy, T. Acharya)

4. Co-Principal
Investigator, *Delay Fault Models and Test Generation for Power Supply *

* Noise,* funded by **Intel Corporation,** USA, 2003-2006 (PI: S. Sur-Kolay)

5. Co-Principal Investigator, *Center for Soft Computing Research: A
National Facility,* funded by **DST,** New Delhi, 2005-2008 (PI: Sankar K. Pal, Co-PI: M. K. Kundu).

** **

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