VLSI 2006
Frontmatter in hardcopy of Proceedings(includes page numbers for papers)
The International Conference on VLSI Design was started in 1985, as a small workshop at IIT Madras, under the visionary guidance of Dr. Vishwani Agrawal of Auburn University, and Prof. H.N. Mahabala of IIT Madras. From this small start, it has grown into a leading international conference on VLSI design, which draws around 700 attendees, every year, from India and abroad. The proceedings are printed by the IEEE Computer Society Press, USA. The conference is dedicated to all aspects of integrated circuit design, technology, and related computer-aided design (CAD). In the recent years, the natural congruence between VLSI Design and Embedded Systems has led to the international conference on Embedded Systems being held jointly with the VLSI Design conference.
Final Conference Program
Highlights of the Technical Program
Keynote Lectures:
The high walls have crumpled (PDF)
- C.L. Liu, National Tsing Hua University, Taiwan.
65 nm Omnibudsman (PDF)
- Ted Vucurevich, Cadence, USA
ESL - The Next Leadership Opportunity For India? (PDF)
- Alan Naumann, CoWare, USA.
VLSI Design Challenges for Gigascale Integration
- Shekhar Borkar, Intel Corporation, USA.
Banquet Speeches:
Comparison of FPGAs and ASICs for SoC applications (PDF)
- Richard Sevcik, Executive VP, Xilinx
Moore's Law is Unconstitutional (PDF)
- Wally Rhines, Mentor Graphics, USA.
Plenary Talks:
Configurable Processor the building block for SOC (System-On-a-Chip)
- Beatrice Fu, Senior VP, Tensilica
Modeling Usable and Reusable Tranasctors in System Verilog (PDF)
- Janick Bergeron, Synopsys
Optimizing SoC Manufacturability (PDF)
- Yervant Zorian, Virage Logic
Complex Processor Architectures - The Verification Challenge
- Sunil Kakkar, Freescale Semiconductor India Ltd
PANEL DISCUSSION:
Next Generation Design: Is EDA the Weakest Link?
Organizer:
Debasis Bhattacharya, Zenasis Technologies
Moderator:
Rob (Rabindra) K. Roy, Zenasis Technologies
Panelists:
Lorena Anghel, TIMA/INPG, France
Sankar Basu, National Science Foundation, USA
Ashis Dixit, Tensilica, USA
Anshul Kumar, IIT Delhi, India
Mahesh Mehendale, Texas Instruments, India
Michael Nicolaidis, iRoC Technologies, France
Yervant Zorian, Virage Logic, USA
Four parallel technical sessions for presentations :
- 97 regular papers
- 6 embedded tutorials
- 16 short papers
- 23 poster papers
- selected Design contest entries
Tutorials : January 6-7, 2005.
Day 1 Jan. 6, 2005
T1 : Power-Aware reliable microprocessor design (Invited Tutorial)
T2 : High-Speed Interconnect Technology: On-Chip and Off-Chip
T3: Testing Nanometer Integrated Circuits: Myths, Reality and the Road Ahead.
T4: SoC Design Methodology: A Practical Approach.
Day 2 Jan. 7, 2005
T5: Test Methodologies in the Deep Sub-micron Era: Analog, Mixed-Signal and RF.
T6: Recent Advances in Verification, Equivalence Checking & SAT-Solvers.
T7A: Compact MOSFET Models for Low Power Analog CMOS Design.
T7B: Physics and Technology: Towards Low-Power DSM Design.
T8: Architectural, System Level and Protocol Level Techniques for
Power Optimization for Networked Embedded Systems.
An Industry Forum is also being organized as a part of VLSI Design 2005 and ICES-4 where finished designs from industry participants will be discussed, offering a great opportunity for industries to interact with each other and exhibit their achievements. Exhibit stalls and presentations from various industries will further enhance interaction with industry participants. A special Research Scholars forum is also being organized where research scholars will get an opportunity to display their work through Posters and obtain valuable feedback from the conference participants.
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