Professional Activities:

  • Important professional/editorial work:
    • Founding Chair IEEE CEDA India Chapter, 2016 - 2018.
    • Member, Steering Committee International Conference on VLSI Design and International Conference on Embedded Systems
    • General Co-Chair 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016.
    • Member, Steering Committee IEEE Computer Society Annual Symposium on VLSI (ISVLSI).
    • Logic Synthesis and Physical Design Track Chair 27th International Conference on VLSI Design & 14th International Conference on Embedded Systems, 2014.
    • Associate Editor ACM Transactions on Embedded Computing Systems, 2014 - 2020.
    • Associate Editor IEEE Transactions on VLSI Systems, 2007 - 2010.
    • Member Editorial Board, IEE Computers and Digital Techniques, 2005-2007.
    • Member, Steering Committee, IEEE Computer Society Annual Symposium on VLSI, 2011 -
    • Member, Board of Course of Study, Department of Computer Science and Engineering, Indian School of Mines, 2011-2012.
    • Member TPC DAC 2022 59th Design Automation Conference, Track on Physical Design and Verification, Lithography and DFM.
    • Member TPC ICCAD 2018 36th IEEE/ACM International Conference on Computer Aided Design, Track on Partitioning, Placement and Floorplanning.
    • Logic Synthesis and Physical Design Track Chair, 27th International Conference on VLSI Design & 14th International Conference on Embedded Systems, 2014.
    • Member TPC ICCAD 2013 31st IEEE/ACM International Conference on Computer Aided Design, Track on Cell-Library Design, Partitioning, Floorplanning, Placement.
    • Member TPC ICCAD 2012 30th IEEE/ACM International Conference on Computer Aided Design, Track on Partitioning, Placement, and Floorplanning.
    • Member TPC ASPDAC 2012 17th Asia and South Pacific Design Automation Conference, Physical Design Subcommitee.
    • Technical Program Co-Chair IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2011.
    • Publications Chair, Asian Test Symposium, 2011.
    • Track Co-Chair (Low Power Design), 23nd International Conference on VLSI Design \& 10th International Conference on Embedded systems, 2010.
    • Track Co-Chair (Physical Design) 22nd International Conference on VLSI Design, 2009.
    • Technical Program Chair 11th Symposium on VLSI Design & Test, 2007
    • Keynote Chair IEEE National Symposium on Emerging Technologies (WieNSET), 2007
    • Associate Track Chair Platinum Jubilee International Conference on Computing: Theory and Applications, 2007
    • Technical Program Chair 18th International Conference on VLSI Design & 4th International Conference on Embedded systems, 2005
    • Tutorial Co-Chair 13th Int'l Conf. on VLSI Design 2000.
    • Member TPC AICCSA-08 6th ACS/IEEE International Conference on Computer Systems and Applications, Algorithms and Bioinformatics Track
    • Member TPC ICIT 07 11th ACS/IEEE International Conference on Information Technology, Embedded Systems and Hardware Track
    • Member & Session Chair Program Committee, Int'l Conf. on VLSI Design 1997-2012.
    • Member International Conference on Computer-Aided Design, USA 1994 Technical Program Committee (Layout Track).
    • Member & Session Chair Program Committee, VLSI Design & Test Workshops,1998-2012.

  • Academic Administration:
    • Head, Advanced Computing and Microelectronics Unit, 2020 - 2022.
    • Professor-in-Charge Computer and Communication Sciences Division, 2016 - 2018.
    • Chairperson Selection Committee for Admission to the M.Tech.(CS) Programme, 2013.
    • Chairperson Committee for Uniform Calendar at all centres, 2012 - 2013.
    • Member Awards Proposals Committee, 2010 - present
    • Member Committee on Teaching Policies, 2009 - 2012.
    • Member Research Fellow Advisory Committee, Computer and Communication Sciences Division (CCSD), I.S.I. 2003 – 2010.
    • Member Academic Council, 2004-2006, 2009 - present
    • Member I.S.I. Admission committee for B. Stat., 2007, 2009, 2014.
    • Member/Convener of Computer Science Subcommittee/ Convener of Engg. Subcommittee I.S.I. Admission committee for M.Tech. (CS), 2000-2007, 2010-11.
    • Member/Convener of Computer Science Subcommittee/ Convener of Engg. Subcommittee I.S.I. Admission committee for J.R.F. (CCSD) 2000-2003, 2006, 2009-12, 2017.
    • Member M.Tech Dissertation and Industrial Training Committee, 2001-2011
    • Advisor Refresher Course for Engg. College teachers on Design and Analysis of Algorithms, Indian Statistical Institute, February 2002.
    • Co-ordinator Refresher Course for Engg. College teachers on Algorithms for VLSI CAD, Indian Statistical Institute, August 2001.

  • Externally funded Projects as Principal Investigator/Co-Principal Investigator:
    • Principal Investigator, "An efficient framework for ensuring security of FPGA-based application cores in Cloud and IoT environment," (2019 - 2022); funded by SERB DST.
    • Principal Investigator, "Lithography aware physical design automation for below 20nm process technology," India-Taiwan S&T Cooperation programme, Global Innovation & Technology Alliance (GITA).
    • Principal Investigator, "Parallel Implementation of H.264 CODEC" (2010-11); funded by Texas Instruments India Pvt. Ltd.
    • Principal Investigator, "RET-aware Global Routing" (2010- ); funded by IBM Corp., USA.
    • Principal Investigator, "Delay Fault Modeling and Test Generation for Power Supply Noise" (2003 - 2006); funded by Intel Corp., USA Software module for test generation completed.
    • Joint Collaborator, "CORCoP: Compilation and Optimization of Reconfigurable Co-Processors" (1999-2002) with IRISA Rennes, France; funded by Indo-French Centre for the Promotion of Advanced Research.
    • Co-Investigator, "CA-based BIST for Asynchronous Sequential Circuits" (1998-2001) with B.E. College, Howrah; funded by Strategic CAD Laboratories, Intel Corp., USA Software delivered to Intel Corp.

  • Design and development of computer software:
    Software implementation for
    • Cellular automata based Built-in Self test methodology for asynchronous sequential circuits
    • Genetic algorithm for finding Restriction enzyme maps from double digest
    • FPGA placer
    • Test pattern generation for delay faults due to power supply droop noise
    • Intellectual Property protection scheme for VLSI floorplans
    • Fast Floorplanner for FPGAs with Heterogeneous Resources
    • Physical design for quantum logic circuits
    • Error-correction in quantum logic circuits
    • Parallel Implementation of H.264 Codec

  • Other professional activities:
    • Chairperson Internal Complaints Cell, 2018 - 2021.
    • Chairperson Cell for Collaboration with Academia, Industry and Research Laboratories (C-CAIR), 2018 - 2022.
    • Chair Committee for development of new website of ISI.
    • Chair Question Paper Moderation Committee for M. Tech. (CS), 2011, 2013.
    • Member Prospectus Committee, 2006, 2010 - 12.
    • Member Building Works Advisory Committee, 2012 - .
    • Chair ISI Calendar Committee, 2012.
    • Member ISI Space Audit Committee, 2012.
    • Member M. Tech. (CS) Programme Publicity Committee, 2012.
    • Member ISI Annual Report Editorial Board (2000-2003)
    • Member ISI Prospectus Committee, 2006, 2010 - .
    • Member ISI Placement Committee, 2006-2007
    • Member IET, U.K.
    • Academia-Industry Liaison Chair IEEE Women in Engineering (WIE) Affinity Group,Kolkata Section, 2006 – 2008.
    • Vice-Chair IEEE WIE, Kolkata Section, 2009 – 2010.
    • Chair IEEE WIE, Kolkata Section, 2011 – 2012.
    • Member Executive Committee, IEEE Kolkata Section, 2009 – 2013.
    • Member Executive Committee, IEEE Circuits and Systems Chapter, Kolkata Section, 2009 – .
    • Chair, IEEE Women in Engineering Affinity Group, Calcutta Section, 2011 - 2012.