Publications:

  • Ph.D. Thesis : Studies on Nonslicible Floorplans in VLSI Layout Design

  • Edited Books:
    • S. Bhunia, S. Ray and S. Sur-Kolay (eds.): Fundamentals of IP and SoC Security - Design, Verification, and Debug, Springer, February 2017.
    • B. B. Bhattacharya, S. Sur-Kolay, S. C. Nandy, A. Bagchi (eds.), Platinum Jubilee Volume of the Indian Statistical Institute: Algorithms, Architectures and Information Systems Security, World Scientific Press, 2008.
    • S. Sur-Kolay, P. S. Dasgupta, D. Mukhopadhyay and C. P. Ravikumar (eds.), Progress in VLSI Design and Test, Elite Publishing House Pvt. Ltd., New Delhi, 2007.

  • Book Chapters:
    • D. Saha and S. Sur-Kolay, "FPGA-based IP and SoC Security,", in Fundamentals of IP and SoC Security - Design, Verification, and Debug, Springer, 2017.
    • B. Kar, S. Sur-Kolay and C. Mandal, STAIRoute: Global Routing using Monotone Staircase Channels, in Best of ISVLSI 2013, Springer, expected in 2017.
    • S. Sur-Kolay, Floorplanning- Early Approaches, "The Handbook of Algorithms for VLSI Physical Design Automation", CRC Press, C. Alpert, D. Mehta and S. Sapatnekar (eds.), 2009.

  • Technical Articles in Journals and Edited Volumes
    • A. M. Nia, S. Sur-Kolay, A. Raghunathan, and N. K. Jha, ``Wearable Medical Sensor-based System Design: A Survey'', accepted for publication in IEEE Transactions on Multi-Scale Computing Systems, February 2017.
    • A. M. Nia, S. Sur-Kolay, A. Raghunathan, and N. K. Jha, “CABA: Continuous Authentication Based on BioAura,” IEEE Transactions on Computers, Early Access: October 2016, DOI:10.1109/TC.2016.2622262.
    • D. Saha and S. Sur-Kolay, “Embedding of Signatures in Reconfigurable Scan Architecture for Authentication of IPs in SoC,” Proc. IET Computers & Digital Tech- niques, vol. 10, no. 3, 2016, pp. 110-118.
    • A. M. Nia, S. Sur-Kolay, A. Raghunathan, and N. K. Jha, “Physiological Information Leakage: A New Frontier in Health Information Security,” IEEE Transactions on Emerging Topics in Computing, vol. 4, no. 3, 2016, pp. 321-334.
    • A. M. Nia, S. Sur-Kolay, A. Raghunathan, and N. K. Jha, “Energy-Efficient Long- term Continuous Personal Health Monitoring,” IEEE Transactions on Multi-Scale Computing Systems, vol. 1, no. 2, 2015, pp. 85-98.
    • M. Mozaffari-Kermani, S. Sur-Kolay, A. Raghunathan, and N. K. Jha,``Systematic Poisoning Attacks on and Defenses for Biomedical Machine Learning,'' IEEE Journal of Biomedical and Health Informatics (J-BHI), vol. 19, no. 6, 2015, pp.1893-1905. (DOI 10.1109/JBHI.2014.2344095).
    • C. -C. Lin, S. Sur-Kolay and N. K. Jha, ``PAQCS: Physical Design-aware Fault-tolerant Quantum Circuit Synthesis,'' IEEE Transactions on VLSI Systems, vol. 23, no. 7, July 2015, pp. 1221-1234. (DOI: 10.1109/TVLSI.2014.2337302).
    • D. Saha and S. Sur-Kolay, ``Watermarking in Hard Intellectual Property for Pre-Fab and Post-Fab Verification,'' IEEE Transactions on VLSI Systems, vol. 23, no. 5, May 2015, pp. 801-809. (DOI: 10.1109/TVLSI.2014.2322138).
    • G. Das, M. De, S. Kolay, S. C. Nandy and S. Sur-Kolay, ``Approximation Algorithms for maximum independent set of a unit disk graph,'' Information Processing Letters, vol. 115, Issue 3, pp. 439-446, March 2015 (DOI: 10.1016/j.ipl.2014.11.002).
    • S. B. Mandal, A. Chakrabarti and S. Sur-Kolay and, ``Quantum Ternary Circuit Synthesis Using Projection Operations," Journal of Multiple-Valued Logic and Soft Computing, vol. 24, No. 1-4, 2015 (accepted in 2013), pp. 73-92.
    • A. Deb, D. K. Das and S. Sur-Kolay, ``A Modular Design to Synthesize Symmetric Functions using Quantum Quaternary Logic,'' Journal of Low Power Electronics, vol. 10, September 2014, pp.443-454 (DOI:10.1166/jolpe.2014.1340).
    • D. Saha and S. Sur-Kolay, "Secure Public Verification of IP Marks in FPGA Design through a Zero-Knowledge Protocol," IEEE Transactions on VLSI Systems, vol. 20, no. 10, Oct. 2012, pp. 1749-1757. (Early access, August 2011 DOI: 10.1109/TVLSI.2011.2162347).
    • D. Saha and S. Sur-Kolay, "SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection," VLSI Design, vol. 2011, Article ID 731957, 10 pages, 2011. doi:10.1155/2011/731957
    • P. Banerjee, M. Sangtani and S. Sur-Kolay, "Floorplanning for Partially Reconfigurable FPGAs," IEEE Transactions on Computer-Aided Design, vol. 30, Jan. 2011, pp. 8 - 17.
    • P. Banerjee, D. Saha and S. Sur-Kolay, "Cone based Placement for FPGAs," Proc. IET Computers & Digital Techniques, vol. 5, 1, 2011, pp. 49 - 62.
    • D. Saha and S. Sur-Kolay, "Robust Intellectual Property Protection of VLSI Physical Design," Proc. IET Computers & Digital Techniques, vol. 4, Issue 5, 2010, pp. 388-399.
    • D. Mitra, A. Nigam, S. Sur-Kolay, B. B. Bhattacharya, "Test Pattern Generation for Droop Faults," Proc. IET Computers & Digital Techniques, vol. 4, Issue 4, 2010 pp. 274-284.
    • P. Banerjee, S. Sur-Kolay, A. Bishnu, S. Das, S. C. Nandy and S. Bhattacharjee, "FPGA Placement using Space Filling Curves: Theory Meets Practice," ACM Transactions on Embedded Computing Systems, Special Issue on Configuring Algorithms, Processes and Architecture (CAPA), vol. 9, Issue 2, October 2009, pp. 12.1-12.23.
    • A. Chakrabarti and S. Sur-Kolay, "Realization of Quantum Boolean Circuits using Garbage Free Fredkin Operations", International Journal of Computer Sciences and Engineering Systems, vol. 3, no. 3, October 2009, pp. 233-237.
    • S. Mandal, A. Chakrabarti and S. Sur-Kolay, "Design of a Hardware Description Language based Quantum Circuit Simulator", International Journal of Recent Trends in Engineering, vol. 1, no. 3, June 2009, pp. 248-252.
    • P. Banerjee, S. Sur-Kolay, and A. Bishnu, "Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs", IEEE Transactions on Computer-Aided Design, vol. 28, May 2009, pp. 651-661.
    • S. Sur-Kolay, S. Banerjee, S. Mukhopadhyaya, C. A. Murthy, "The Double Digest Problem: finding all solutions", International Journal of Bioinformatics Research and Applications (IJBRA), vol. 5, no. 5, 2009, pp. 570-592.
    • S. Saha, S. Sur-Kolay, P. S. Dasgupta and S. Bandyopadhyay, "MAkE: Multiobjective Algorithm for k-way Equipartitioning of a Point Set", Applied Soft Computing, vol. 9, Issue 2, March 2009, pp. 711-724.
    • D. Mitra, S. Sur-Kolay and B. B. Bhattacharya, "On Droop Sensitivity of Stuck-at Fault Tests", IET Computers and Digital Techniques, 2009, vol. 3, Issue 2, pp. 175-183.
    • I. Vishnuvardhan, S. K. Dey, S. Sur-Kolay, D. Mitra, B.B. Bhattacharya, "An Efficient Simulator for Power Grid Analysis in VLSI Chips", AMSE Best of Book Journal (in press) 2008.
    • A. Chakrabarti and S. Sur-Kolay, "Nearest Neighbour based Synthesis of Quantum Boolean Circuits", Engineering Letters, vol. 15 Issue 2, December 2007, pp. 356-361.
    • D. Saha, P. S. Dasgupta, S. Sen Sarma and S. Sur-Kolay, "A Novel Scheme for IP Security in Physical Design", International Journal of Computer Science and Information Technology, vol. 1, December 2007, pp. 58 -67.
    • S. Majumder, S. Sur-Kolay B. B. Bhattacharya and Swarup Das, "Hierarchical Partitioning of VLSI Floorplans by Staircases", ACM Transactions on Design Automation of Electronic Systems, vol. 12, no. 1, January 2007, pp. 141-159.
    • A. Chakrabarti and S. Sur-Kolay, "The Essence of Quantum Computing", Young Horizon Computing and Informatics, vol. 1, December 2006, pp: 42-45.
    • S. Das, S. Sur-Kolay and B. B. Bhattacharya, "Manhattan-diagonal routing of channels and switchboxes", ACM Transactions on Design Automation of Electronic Systems, vol. 9, no. 1, January 2004, pp. 75-104.
    • P. S. Dasgupta and S. Sur-Kolay, "Slicibility Conditions of Rectangular Graphs and Their Applications to Floorplan Optimization," ACM Transactions on Design Automation of Electronic Systems, vol. 6, No. 4, October 2001, pp. 447-470.
    • P. S. Dasgupta, S. Sur-Kolay and B. B. Bhattacharya, "A Unified Approach to Topology Generation and Optimal Sizing of Floorplans", IEEE Transactions on Computer-Aided Design, Vol. 17, No. 2, February 1998, pp. 126-135.
    • S. Sur-Kolay, S. Banerjee, S. Mukhopadhyaya and C. A. Murthy, "A Genetic Algorithm for the Double Digest Problem", Lecture Notes in Computer Science 3776, 2005, Springer, pp. 623-629.
    • S. Goswami and S. Sur-Kolay, "Virtual Molecular Computing: Emulating DNA molecules", Lecture Notes in Computer Science 3326, Springer, 2004, pp. 95-101.
    • A. Roychoudhury and S. Sur-Kolay, "Efficient Algorithms for Vertex Arboricity of Planar Graphs," Lecture Notes in Computer Science, No. 1026, eds. G.Goos, J. Hartmanis and J. van Leeuwen, Springer, 1995, pp. 37-51.
    • S. Sur-Kolay and B. B. Bhattacharya, "Inherent Nonslicibility of Rectangular Duals in VLSI Floorplanning," Lecture Notes in Computer Science, No. 338, eds. G.Goos and J. Hartmanis, Springer Verlag, 1988, pp. 88-107.
    • S. Kundu, C. Tirumurti, Y. Chang, S. Sur-Kolay, "On testing of Microprocessors for Power Supply related Failures", IEEE Trans. on VLSI Systems (under revision), 2008

  • Technical Articles in Refereed Conference Proceedings
    • R. Majumdar, S. Ghosh and S. Sur-Kolay, "A Method to Reduce Resources for Quan- tum Error Correction," accepted for Proc. 9th Conference on Reversible Computation (RC), July 6-7, 2017.
    • D. Saha and S. Sur-Kolay, "Multi-objective optimization of placement and assignment of TSVs in 3D ICs," in Proc. 30th International Conference on VLIS Design, January 2017.
    • S. Basu, A. K. Chakrabarti and S. Sur-Kolay, ”An Efficient Synthesis Method for Ternary Reversible Logic,” Proc. ISCAS 2016, pp. 2306-2309.
    • B. Kar, S. Sur-Kolay and C. Mandal, ”A Novel EPE aware Hybrid Global Route Planner after Floorplanning,” Proc. 29th Internatinal Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016, pp. 585-596.
    • S. Paul, P. Banerjee and S. Sur-Kolay, ”Flare Reduction in EUV Lithography by Perturbation of Wire Segments,” Proc. 23rd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Daejeon, Korea, Oct. 5-7, 2015.
    • B. Kar, S. Sur-Kolay and C. Mandal, “ A New Method for Defining Monotone Staircases in VLSI Floorplans,” Proc. IEEE Computer Society Annual Symposium on VLSI 2015 (ISVLSI 2015), Montpellier, France, July 8-10, 2015.
    • S. Saha, B. Kar and S. Sur-Kolay, ``A Novel Architecture for QPSK Modulation based on Time-Mode Signal Processing,'' Proc. 18th International Symposium on VLSI Design and Test, July 16-18, 2014.
    • S. B. Mandal. A. Chakrabarti and S. Sur-Kolay, ``Synthesis of Ternary Grover's Algorithm," Proc. IEEE 44$^{th}$ International Symposium on Multiple-Valued Logic - ISMVL 2014, Bremen, Germany, May 19-21, 2014, pp. 184-189.
    • A. Bhattacharya, A. Banerjee, S. Sur-Kolay: Energy-Aware H.264 Decoding. ICDCIT 2014, pp. 200-211.
    • B. Kar, S. Sur-Kolay and C. Mandal, "Global Routing using Monotone Staircases with Minimal Bends," Proc. 27th International Conference on VLSI Design, Jan. 5-9, 2014, Mumbai, pp. 369-374.
    • A. Deb, D. Das and S. Sur-Kolay, " Modular Design for Symmetric Functions using Quantum Quaternary Logic," Proc. Fourth International Symposium on Electronic System Design, Dec. 12-13, 2013, Singapore.
    • D. Saha and S. Sur-Kolay, "Updation of Activation Sequence of a Chip after its Deployment for Access Control," Procedia Technology, Elsevier, 2013.
    • B. Kar, S. Sur-Kolay and C. Mandal, "STAIRoute: Global Routing using Monotone Staircase Channels," Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Springer, 2013.
    • A. Bhattacharya, A. Banerjee, S. Sur-Kolay, P. Basu and B. J. Karmakar, "A cache-aware strategy for H.264 decoding on multi-processor architectures," Proc. 17th Int'l Symposium on VLSI Design and Test (VDAT), Springer, 2013.
    • D. Saha and S. Sur-Kolay, "Planarization of metal layers in a chip based on Voronoi diagram," Proc. 5th International Conference on Computers and Devices for Communication (CODEC) 2012.
    • B. Kar, S. Sur-Kolay, S. H. Rangarajan, C. Mandal, "A Faster Hierarchical Balanced bipartitioner for VLSI Floorplans using Monotone Staircase Cuts," Proc. 16th International Symposium on VLSI Design and Test, July 1-4, 2012.
    • S. B. Mandal. A. Chakrabarti and S. Sur-Kolay, "A Synthesis Method for Quaternary Quantum Logic Circuits," Proc. 16th International Symposium on VLSI Design and Test, July 1-4, 2012.
    • A. Datta and S. Sur-Kolay, "TSV –aware Scan Chain Re-ordering for 3D ICs," IEEE Annual Symposium on VLSI (ISVLSI), 2011, Chennai, July 4-6.
    • S. Bhowmick, O. Tiwari, S. Sur-Kolay and B. B. Bhattacharya, "Test pattern generation for Multi-cycle Power Droop using SAT solver," European Test Symposium 2011, Trondheim, Norway, May 23-27.
    • S. B. Mandal, A. Chakravarti and S. Sur-Kolay, "Synthesis techniques for Ternary Quantum Logic", Proc. IEEE 41st International Symposium on Multiple-Valued Logic (ISMVL) 2011, Tuusla, Finland, May 23-25.
    • S. Mukhopadhyay, P. Banerjee and S. Sur-Kolay, "Balanced Bipartitioning of a multi-weighted hypergraph for heterogenous FPGAs,", Proc. VII Southern Programmable Logic Conference, Cordoba, Argentina, April 13-15, 2011.
    • S. Kolay, S. C. Nandy and S. Sur-Kolay, "2-Factor Approximation Algorithm for Computing Maximum Independent Set of a Unit Disk Graph," Proc. 26th European Workshop on Computational Geometry (EuroCG'10), March 2010, pp. 205-208.
    • D. Saha and S. Sur-Kolay, "A Unified Approach for IP Protection across Design Phases in a Packaged Chip," Proc. 23rd International Conference on VLSI Design, January 5-7, 2010, pp. 105-110.
    • D. Saha and S. Sur-Kolay, "Secure Leakage-Proof Public Verification of IP Marks in VLSI Physical Design," Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI'09), Tampa, Fl. USA, May 13-15, 2009, pp. 169 - 174.
    • P. Banerjee, S. Sur-Kolay, "Floorplanning for Partial Reconfiguration in FPGAs," Proc. 22nd International Conference on VLSI Design, Jan. 5-7, 2009, pp. 125 - 130.
    • D. Saha and S. Sur-Kolay, "Encoding of Floorplans through Deterministic Perturbation," Proc. 22nd International Conference on VLSI Design, Jan. 5-7, 2009, pp. 315 - 320.
    • D. Saha and S. Sur-Kolay, "An Analytical Approach to Direct IP Protection of VLSI Floorplans," Proc. Third IEEE International Conference on Industrial and Information Systems, December 8-10, 2008, pp. 1 - 6.
    • A. Chakrabarti and S. Sur-Kolay, "Design of Quantum Adder Circuits and Evaluating Their Error Performance," Proc. International Conference on Electronic Design, December 1-3, Penang, Malaysia, 2008, pp. 1 - 6.
    • D. Saha and S. Sur-Kolay, "Fast Robust Intellectual Property Protection for VLSI Physical Design", Proc. 10th International Conference on Information Technology, 2007, pp. 1-5. (Best Paper Award winner).
    • A. Chakrabarti and S. Sur-Kolay, "Rules for Synthesizing Quantum Boolean Circuits using Minimized Nearest-Neighbour Templates", Proc. 15th International Conference on Advanced Computing and Communications (ADCOM) 2007, pp. 183 - 189.
    • I. Vishnu Vardhan, S. K. Dey, S. Sur-Kolay, D. Mitra and B. B. Bhattacharya, "An efficient simulator for power grid analysis in VLSI Chips", Proc. International Conference on Modeling and Simulation, 2007, pp. 646-650.
    • D. Saha, P. Banerjee and S. Sur-Kolay, "Fast I/O Pad Placement in FPGAs", Proc. 11th Symposium on VLSI Design and Test, 2007, pp.153-161.
    • D. Mitra, A. Nigam, S. K. Dey, S. Sur-Kolay and B. B. Bhattacharya, "Testing Droop Faults in Full Scan Circuits", Proc. 11th Symposium on VLSI Design and Test, 2007, pp. 185-195.
    • P. Banerjee and S. Sur-Kolay, "Faster Placer for Island-style FPGAs", Proc. International Conference on Computing: Theory and Applications, (ICCTA), IEEE CS Press, USA, March 2007, pp. 117-121.
    • D. Saha, P. S. Dasgupta, S. Sur-Kolay and S. Sensarma, "A novel scheme for encoding and watermark embedding in VLSI physical design for IP protection", Proc. International Conference on Computing: Theory and Applications, (ICCTA), IEEE CS Press, USA, March 2007, pp. 111-116.
    • P. Banerjee, S. Sur-Kolay and A. Bishnu, "Floorplanning in Modern FPGAs", Proc. IEEE 20th International Conference on VLSI Design, Bangalore, Jan. 6-10,2007, pp. 893-898.
    • A. Chakrabarti, S. Sur-Kolay and M. Malakar, "A Programming Model for Quantum Circuit Simulator", Proc. IEEE International Conference on Devices and Electronic Communications (CODEC'06), 2006, Dec. 18-20.
    • S. Saha, S. Sur-Kolay, S. Bandyopadhyay and P. S. Dasgupta, "Multiobjective genetic algorithm for k-way equipartitioning of a point set with application to CAD-VLSI", Proc. 9th IEEE International Conference on Information Technology, Application Specific Software and Hardware Systems Track, Dec.18-21 2006, pp. 281 - 284.
    • A. Chakrabarti and S. Sur-Kolay, "Reversible Logic Synthesis of Boolean Circuits in Quantum Domain", Proc. IEEE Electronic and Photonic Materials, Devices and Systems" (EPMDS 2006), 2006.
    • D. Mitra, S. Sur-Kolay, B. B.Bhattacharya, S. T. Zacharíah and S. Kundu, "Test Pattern generation for Power Supply Droop Faults", Proc. IEEE 19th International Conference on VLSI Design, 2006, pp. 343-348.
    • P. Banerjee, S. Bhattacharjee, S. Sur-Kolay, S. Das and S. C. Nandy, "Fast FPGA Placement using Space-filling Curve", Proc. 15th IEEE International Conference on Field-Programmable Logic and Applications, IEEE CS Press, Tampere, Finland, August 24-26, 2005, pp. 415 - 420.
    • S. Saha, S. Sarkar, V. K. Tandon and S. Sur-Kolay, "Comparative study of logic optimization in FPGA", in Proc. 9th VLSI Design and Test Symposium, Bangalore, August 11-13, 2005, pp. 451- 455.
    • A. Chakrabarti and S. Sur-Kolay, "A Novel Method for Synthesis of Reversible Quantum Circuits", Proc. The 2005 International Conference on Computer Design, (CDES-05), Las Vegas, June 2005.
    • S. Majumder, S. Sur-Kolay, S. C. Nandy, B. B. Bhattacharya and B. Chakraborty, "Hot spots and zones in a chip: a geometrician's view", Proc. IEEE 18th International Conference on VLSI Design and 4th International Conference on Embedded Systems, Kolkata, Jan. 3-7, 2005, IEEE CS Press, pp. 691 - 696.
    • C. Tirumurti, S. Kundu, Y-S. Chang, S. Sur-Kolay, "A Modeling Approach For Addressing Power Supply Switching Noise Related Failures of Integrated Circuits", Proc. IEEE/ACM Design Automation and Test in Europe (DATE), IEEE CS Press, Feb. 16-20, 2004, pp. 1078-1083.
    • A. Chakrabarti and S. Sur-Kolay, "Adder Circuits in Quantum Domain", Proc. All India Seminar on Recent Advances in VLSI, The Institute of Engineers (India), 2004, pp. 14-17.
    • A. Chakrabarti and S. Sur-Kolay, "Mathematical Model for Quantum Computing", Proc. IEEE International Conference on Devices and Electronic Communications (CODEC ’04), Kolkata, Jan. 1-4, 2004.
    • S. Sur-Kolay, S. Banerjee and C. A. Murthy, "Flavours of Traveling Salesman Problem in VLSI Design", Proc. Indian International Conference on Artificial Intelligence, Hyderabad, Dec. 18-20, 2003, pp. 656-667.
    • S. Sur-Kolay, S. Kundu, C. Tirumurti, S. Zachariah and Y. Chang, "Analysis and Modeling of Power Supply related failures", Proc. European Test Workshop, IEEE CS Press, Maastricht, May 25-27, 2003.
    • A. Chakrabarti and S. Sur-Kolay, "Two register model for solving quantum factoring problem", Horizons of Telecommunications, Kolkata, Feb. 2003.
    • P. Banerjee and S. Sur-Kolay, "An Accelerator for FPGA Placement", Proc. VLSI Design and Test Workshops, August 2002, pp. 340-347.
    • S. Derrien, S. Rajopadhye and S. Sur-Kolay, "Combining Instruction and Loop Parallelism in array synthesis for FPGAs," Proc. ACM International Symposium on System Synthesis, ACM, Montreal, Canada, Sep. 30 - Oct. 3, 2001, pp. 165-170.
    • S. Derrien, S. Rajopadhye and S. Sur-Kolay, "Combining Instruction and Loop Level Parallelism for FPGAs", Proc. 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, (FCCM '01), IEEE CS Press, California, April 29 - May 2, 2001, pp. 273-282.
    • S. Majumder, S. Sur-Kolay, S. C. Nandy and B. B. Bhattacharya, "Area- (Number-) Balanced Hierarchy of Staircase Channels with minimum crossing nets", Proc. IEEE/ACM International Conference on Circuits and Systems (ISCAS 2001), May 6-9, 2001, Sydney, Australia, IEEE Press, pp. 395-398.
    • K. Sinha, S. Sur-Kolay, P. S. Dasgupta and B. B. Bhattacharya, "Partitioning Routing area into zones with distinct pins", Proc. 13th IEEE International Conference on VLSI Design, Jan. 3-7, 2001, Bangalore, IEEE CS Press, pp. 345-350.
    • S. Sur-Kolay, P. Pal Chaudhuri, M. Roncken, K. Stevens and R. Roy, "FsimAc : A fault simulator for asynchronous sequential circuits", Proc. IEEE 9th Asian Test Symposium, Dec. 4-6, 2000, Taipei, IEEE CS Press, pp. 114-119.
    • S. Derrien, S. Sur-Kolay and S. Rajopadhye, "Optimal Partitioning for FPGA based regular array Implementation", Proc. IEEE International Conference on Parallel Computing in Electrical Engineering (PARELEC 2000), Trois-Rivieres, Quebec, Canada, August 27-30, 2000, IEEE Press, pp. 155-159.
    • S. Bhunia, S. Majumder, A. Sircar, S. Sur-Kolay and B. B. Bhattacharya, "Topological Routing amidst Polygonal Obstacles", Proc.IEEE International Conference on VLSI Design, IEEE CS Press, Jan. 2000, pp. 274 - 279.
    • S. Ghose, S. Sur-Kolay and B. B. Bhattacharya, "VLSI chips on Three-dimensional Closed Surfaces", Proc. VLSI Design and Test Workshop, August 1998.
    • P. Mahalingam, S. Sur-Kolay, S. C. Nandy and B. B. Bhattacharya, "Topological Routing in the presence of Polygonal Obstacles", Proc. VLSI Design and Test Workshop, August 1998.
    • P. S. Dasgupta and S. Sur-Kolay, "Slicible Floorplans using Adjacency Graph Transformations", 1st Workshop on VLSI Physical Design, Chennai, January 1998.
    • S. Majumder, S. Sur-Kolay and B.B. Bhattacharya, "Routing-driven Floorplanning by Hierarchical Rectangular Dualization", 1st Workshop on VLSI Physical Design, Chennai, January 1998.
    • S. Das, S. Sur-Kolay and B. B. Bhattacharya, "Routing of L-shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model", Proc. IEEE International Conference. on VLSI Design, IEEE CS Press, January 1998, pp. 65-70.
    • P. S. Dasgupta and S. Sur-Kolay, "Slicibility of Rectangular Graphs and Floorplan Optimization", Proc. ACM-SIGDA International Symposium on Physical Design, (1997), ACM, pp. 150-155.
    • P. S. Dasgupta, S. Sur-Kolay and B. B. Bhattacharya, "A Unified Approach to Topology Generation and Area Optimization of General Floorplans", Digest of IEEE/ACM International Symposium on Computer-Aided Design, (1995), IEEE CS Press, pp. 712-715.
    • P. S. Dasgupta, S. Sur-Kolay and B. B. Bhattacharya, "VLSI Floorplan Generation and Area Optimization using AND-OR Graph Search", Proc. IEEE International Conference on VLSI Design, IEEE CS Press, January 1995, pp. 370 - 375.
    • P. S. Dasgupta, S. Sur-Kolay and B.B. Bhattacharya, "VLSI Floorplan Design using AI techniques", Proc. International Workshop on Applications of Artificial Intelligence, March (1994).
    • S. Sur-Kolay and B. B. Bhattacharya, "Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning", Proc. 29th ACM/IEEE Design Automation Conference, Anaheim CA., USA, (1992), IEEE CS Press, pp. 69 - 74.
    • S. Sur-Kolay and B. B. Bhattacharya, "The Cycle Structure of Channel Graphs in Nonslicible Floorplans and A Unified Algorithm for Feasible Routing Order", Proc. IEEE International Conference on Computer Design (ICCD), Cambridge, MA. USA, (1991), IEEE CS Press, pp. 524 - 527.
    • S. Sur-Kolay and B. B. Bhattacharya, "On the Family of Inherently Nonslicible Floorplans in VLSI Layout Design", Proc. IEEE International Symposium on Circuits and System (ISCAS), Singapore, (1991), IEEE Press, pp. 2850 - 2853.

  • Technical Reports:
    • S. Biswas, S. Sur-Kolay and S.C. Nandy, "Greedy heuristic for Zone partitioning of pins on a placement", ACMU/2002/01.
    • G. Das, S. C. Nandy and S. C. Nandy, "Rectilinear non-crossing shortest paths between pairs of terminals", ACMU/2002/02.
    • A. Roychowdhury and S. Sur-Kolay, "On Star-coloring of grids and torii", ACMU/2001/01.
    • J. Mukherjee and S. Sur-Kolay, "Fast Technology Mapper FPGAs", 2001, ACMU/2002/02.
    • S. Ghosh and S.Sur-Kolay, "Leader Election in Star graphs", 2001, ACMU/2002/03.
    • G. Banerjee, K. Dasgupta and S. Sur-Kolay, "The Moat Routing Problem", JU/CSE/1997/01.
    • A. Jas, A. Majumder and S. Sur-Kolay, "Efficient Algorithms for Domatic Number Problem of Split Graphs and Permutation Graphs", JU/CSE/1996/01.
    • S. Chakraborti, C. A. Mandal and S. Sur-Kolay, "Simulated Annealing Based Integration of Operator Binding and Placement in VLSI Design", JU/CSE/1995/01.